AMD Phenom 8650 Triple-Core HD8650WCGHBOX User Manual
Product codes
HD8650WCGHBOX
46
Product Errata
41322
Rev. 3.16 February 2008
Revision Guide for AMD Family 10h Processors
315 FST and FSTP Instructions May Calculate Operand Address in
Incorrect Mode
Description
A Floating-Point Store Stack Top (FST or FSTP) instruction in 64-bit mode that is followed shortly
by an instruction that changes to compatibility mode may incorrectly calculate the operand address
using compatibility mode. Also, an FST or FSTP instruction in compatibility mode that is followed
shortly by an instruction that changes to 64-bit mode may incorrectly calculate the operand address
using 64-bit mode.
by an instruction that changes to compatibility mode may incorrectly calculate the operand address
using compatibility mode. Also, an FST or FSTP instruction in compatibility mode that is followed
shortly by an instruction that changes to 64-bit mode may incorrectly calculate the operand address
using 64-bit mode.
The incorrect mode for address calculation is only used under highly specific internal timing
conditions and when the Underflow Mask bit (FCW bit 4) is set and the data to be stored by the FST
or FSTP instruction is a denormalized (tiny) number.
conditions and when the Underflow Mask bit (FCW bit 4) is set and the data to be stored by the FST
or FSTP instruction is a denormalized (tiny) number.
Potential Effect on System
The processor may store to an incorrect address. This may cause an unexpected page fault or
unpredictable system behavior. This sequence has not been observed in any production software.
unpredictable system behavior. This sequence has not been observed in any production software.
Suggested Workaround
Contact your AMD representative for information on a BIOS update.
Fix Planned
Yes