Microchip Technology 25AA02E48T-I/OT Memory IC SOT-23-6 2 K 256 x 8 25AA02E48T-I/OT Data Sheet
Product codes
25AA02E48T-I/OT
25AA02E48/25AA02E64
DS20002123D-page 12
2008-2013 Microchip Technology Inc.
2.7
Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
2.8
Power-On State
The 25AA02EXX powers on in the following state:
• The device is in low-power Standby mode
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
TABLE 2-4:
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
(pin 3)
WEL
(SR bit 1)
Protected Blocks
Unprotected Blocks
STATUS Register
0 (low)
x
Protected
Protected
Protected
1 (high)
0
Protected
Protected
Protected
1 (high)
1
Protected
Writable
Writable
x = don’t care