STMicroelectronics M24C64-WMN6TP Memory IC M24C64-WMN6TP Data Sheet
Product codes
M24C64-WMN6TP
DC and AC parameters
M24C64-W M24C64-R M24C64-F
DocID16891 Rev 28
Table 17. 1 MHz AC characteristics
Symbol
Alt.
Parameter
(1)
1. Only for M24C64 devices identified by the process letter K.
Min.
Max. Unit
f
C
f
SCL
Clock frequency
0
1
MHz
t
CHCL
t
HIGH
Clock pulse width high
260
-
ns
t
CLCH
t
LOW
Clock pulse width low
500
-
ns
t
XH1XH2
t
R
Input signal rise time
(2)
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when f
C
< 1 MHz.
ns
t
XL1XL2
t
F
Input signal fall time
ns
t
QL1QL2
(3)
3. Characterized only, not tested in production.
t
F
SDA (out) fall time
20
(4)
4. With C
L
= 10 pF.
120
ns
t
DXCX
t
SU:DAT
Data in setup time
50
-
ns
t
CLDX
t
HD:DAT
Data in hold time
0
-
ns
t
CLQX
(5)
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
t
DH
Data out hold time
100
-
ns
t
CLQV
(6)
6. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or
0.7 V
CC
, assuming that the Rbus × Cbus time constant is within the values specified in
.
t
AA
Clock low to next data valid (access time)
-
450
ns
t
CHDL
t
SU:STA
Start condition setup time
250
-
ns
t
DLCL
t
HD:STA
Start condition hold time
250
-
ns
t
CHDH
t
SU:STO
Stop condition setup time
250
-
ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
condition
500
-
ns
t
WLDL
7. WC=0 set up time condition to enable the execution of a WRITE command.
t
SU:WC
WC set up time (before the Start condition)
0
-
µs
t
DHWH
(8)(3)
8. WC=0 hold time condition to enable the execution of a WRITE command.
t
HD:WC
WC hold time (after the Stop condition)
1
-
µs
t
W
t
WR
Write time
-
5
ms
t
Pulse width ignored (input filter on SCL and
SDA)
SDA)
-
80
ns