Microchip Technology IC MCU FLASH 4K PIC16LF88-I/P DIP-18 MCP PIC16LF88-I/P Information Guide
Product codes
PIC16LF88-I/P
©
2007 Microchip Technology Inc.
DS80233C-page 3
TIMER1 MODULE
1.
Module: Timer1 (Asynchronous Counter)
When writing to the TMR1H register, under
specific conditions, it is possible that the TMR1L
register will miss a count while connected to the
external oscillator via the T1OSO and T1OSI pins.
specific conditions, it is possible that the TMR1L
register will miss a count while connected to the
external oscillator via the T1OSO and T1OSI pins.
When Timer1 is started, the circuitry looks for a
falling edge before a rising edge can increment the
counter. Writing to the TMR1H register is similar to
starting Timer1; therefore, the former logic stated
falling edge before a rising edge can increment the
counter. Writing to the TMR1H register is similar to
starting Timer1; therefore, the former logic stated
applies any time the TMR1H register is written. If
the TMR1H register is not completely written to
during the high pulse of the external clock, then the
TMR1L register will miss a count due to the circuit
operation stated previously. The high pulse of a
32.768 kHz external clock crystal yields a 15.25
the TMR1H register is not completely written to
during the high pulse of the external clock, then the
TMR1L register will miss a count due to the circuit
operation stated previously. The high pulse of a
32.768 kHz external clock crystal yields a 15.25
μ
s
window for the write to TMR1H to occur. The
amount of instructions that can be executed within
this window is frequency dependent, as shown in
Table 1 below.
amount of instructions that can be executed within
this window is frequency dependent, as shown in
Table 1 below.
TABLE 1:
FREQUENCY DEPENDENT INSTRUCTION EXECUTION AMOUNTS
Work around
Operating Conditions: F
OSC
≥
4 MHz, no wake-ups
from Sleep, Timer1 interrupt enabled, global
interrupts enabled.
interrupts enabled.
The code excerpts in Example 1, Example 2 and
Example 3 show how the TMR1H register can be
updated while the external clock (32.768 kHz) is
still on its high pulse.
Example 3 show how the TMR1H register can be
updated while the external clock (32.768 kHz) is
still on its high pulse.
The importance of the code examples is that the
bold instructions are executed within the first
15.25
bold instructions are executed within the first
15.25
μ
s high pulse on the external clock after the
Timer1 overflow occurred. This will allow the
TMR1L register to increment correctly.
TMR1L register to increment correctly.
F
OSC
T
CY
(
μ
s)
T
CY
within 15.25
μ
s
1 MHz
4
3.81
2 MHz
2
7.63
4 MHz
1
15.25
8 MHz
0.5
30.5
16 MHz
0.25
61
20 MHz
0.2
76.25
40 MHz (PIC18)
0.1
152.5