Microchip Technology IC MCU OTP 2KX PIC17C42A-16/P DIP-40 MCP PIC17C42A-16/P Data Sheet

 

DS30412C-page 22

 

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 1996 Microchip Technology Inc.

 

The Interrupt Status/Control register (INTSTA) records
the individual interrupt requests in flag bits, and con-
tains the individual interrupt enable bits (not for the
peripherals).

The PEIF bit is a read only, bit wise OR of all the periph-
eral flag bits in the PIR register (Figure 5-4).

Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is
cleared, the device will vector to the reset address
(0x00).

When disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).  

 

T0IF, INTF, T0CKIF, or PEIF will be set by
the specified condition, even if the corre-
sponding interrupt enable bit is clear (inter-
rupt disabled) or the GLINTD bit is set (all
interrupts disabled).

 

R - 0

R/W - 0 R/W - 0 R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

 

R = Readable bit
W = Writable bit
- n = Value at POR reset

 

bit7

bit0

bit 7:

 

: Peripheral Interrupt Flag bit

This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
1 = A peripheral interrupt is pending
0 = No peripheral interrupt is pending

bit 6:

 

: External Interrupt on T0CKI Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).
1 = The software specified edge occurred on the RA1/T0CKI pin
0 = The software specified edge did not occur on the RA1/T0CKI pin

bit 5:

 

: TMR0 Overflow Interrupt Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).
1 = TMR0 overflowed
0 = TMR0 did not overflow

bit  4:

 

: External Interrupt on INT Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).
1 = The software specified edge occurred on the RA0/INT pin
0 = The software specified edge did not occur on the RA0/INT pin

bit 3:

 

: Peripheral Interrupt Enable bit

This bit enables all peripheral interrupts that have their corresponding enable bits set.
1 = Enable peripheral interrupts
0 = Disable peripheral interrupts

bit 2:

 

: External Interrupt on T0CKI Pin Enable bit

1 = Enable software specified edge interrupt on the RA1/T0CKI pin
0 = Disable interrupt on the RA1/T0CKI pin

bit 1:

 

: TMR0 Overflow Interrupt Enable bit

1 = Enable TMR0 overflow interrupt
0 = Disable TMR0 overflow interrupt

bit 0:

 

: External Interrupt on RA0/INT Pin Enable bit

1 = Enable software specified edge interrupt on the RA0/INT pin
0 = Disable software specified edge interrupt on the RA0/INT pin