Microchip Technology IC MCU OTP 4K PIC16C74B-20/L PLCC-44 MCP PIC16C74B-20/L Data Sheet
Product codes
PIC16C74B-20/L
1998-2013 Microchip Technology Inc.
DS30605D-page 21
PIC16C63A/65B/73B/74B
4.2.2.3
INTCON Register
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
REGISTER 4-3:
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt
.
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE:
Global Interrupt Enable bit
1
= Enables all unmasked interrupts
0
= Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1
1
= Enables all unmasked peripheral interrupts
0
= Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1
1
= Enables the TMR0 interrupt
0
= Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1
1
= Enables the RB0/INT external interrupt
0
= Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1
1
= TMR0 register has overflowed (must be cleared in software)
0
= TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1
1
= The RB0/INT external interrupt occurred (must be cleared in software)
0
= The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1
1
= At least one of the RB7:RB4 pins changed state
(1)
0
= None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will exist until PORTB is read. After reading PORTB, the RBIF
flag bit can be cleared.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown