Microchip Technology IC MCU OTP 4K PIC16C74B-20/L PLCC-44 MCP PIC16C74B-20/L Data Sheet
Product codes
PIC16C74B-20/L
1998-2013 Microchip Technology Inc.
DS30605D-page 47
PIC16C63A/65B/73B/74B
8.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
The input clock (F
OSC
/4) has a prescale option of 1:1,
1:4, or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
(T2CON<2>) to minimize power consumption.
Register 8-1 shows the Timer2 control register.
Additional information on timer modules is available in
the PIC
the PIC
®
Mid-Range MCU Family Reference Manual
(DS33023).
8.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, BOR, MCLR Reset, or
WDT Reset)
TMR2 is not cleared when T2CON is written.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate the
shift clock.
SSP module, which optionally uses it to generate the
shift clock.
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
REGISTER 8-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2
Sets Flag
TMR2 reg
Output
(1)
RESET
Postscaler
Prescaler
PR2 reg
2
F
OSC
/4
1:1
1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note
1: TMR2 register output can be software selected by the
SSP module as a baud clock.
to
T2OUTPS3:
T2OUTPS0
T2OUTPS0
T2CKPS1:
T2CKPS0
T2CKPS0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1
TOUTPS0
TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000
0000
= 1:1 Postscale
0001
= 1:2 Postscale
0010
= 1:3 Postscale
•
•
•
1111
•
•
1111
= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1
1
= Timer2 is on
0
= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00
00
= Prescaler is 1
01
= Prescaler is 4
1x
= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown