Microchip Technology IC MCU FLASH PIC16F874-20I/P DIP-40 MCP PIC16F874-20I/P Data Sheet
Product codes
PIC16F874-20I/P
PIC16F87X
DS30292D-page 12
1998-2013 Microchip Technology Inc.
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER
FILE
FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register (FSR).
rectly through the File Select Register (FSR).
RP1:RP0
Bank
00
0
01
1
10
2
11
3
Note:
EEPROM Data Memory description can be
found in Section 4.0 of this data sheet.
found in Section 4.0 of this data sheet.