Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
PIC18F87K22 FAMILY
DS39960D-page 114
2009-2011 Microchip Technology Inc.
7.2.2
TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an eight-bit register
mapped into the SFR space. The Table Latch register
is used to hold 8-bit data during data transfers between
program memory and data RAM.
mapped into the SFR space. The Table Latch register
is used to hold 8-bit data during data transfers between
program memory and data RAM.
7.2.3
TBLPTR – TABLE POINTER
REGISTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the User ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the User ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD
and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways, based on the
table operation. These operations are shown in
table operation. These operations are shown in
and only affect the low-order 21 bits.
7.2.4
TABLE POINTER BOUNDARIES
The TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into the TABLAT.
When a TBLWT is executed, the six LSbs of the Table
Pointer register (TBLPTR<5:0>) determine which of
the 64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into the TABLAT.
When a TBLWT is executed, the six LSbs of the Table
Pointer register (TBLPTR<5:0>) determine which of
the 64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.
TABLE 7-1:
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 7-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21
16
15
8
7
0
TABLE ERASE/WRITE
TABLE WRITE
TABLE READ – TBLPTR<21:0>
TBLPTRL
TBLPTRH
TBLPTRU
TBLPTR<5:0>
TBLPTR<21:6>