Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
PIC18F87K22 FAMILY
DS39960D-page 162
2009-2011 Microchip Technology Inc.
11.5
RCON Register
The RCON register contains the bits used to determine
the cause of the last Reset, or wake-up from Idle or
Sleep modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
the cause of the last Reset, or wake-up from Idle or
Sleep modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 11-22: RCON: RESET CONTROL REGISTER
R/W-0
R/W-1
R/W-1
R/W-1
R-1
R-1
R/W-0
R/W-0
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IPEN:
Interrupt Priority Enable bit
1
= Enable priority levels on interrupts
0
= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6
SBOREN:
Software BOR Enable bit
For details of bit operation, see
.
bit 5
CM:
Configuration Mismatch Flag bit
1
= A Configuration Mismatch Reset has not occurred
0
= A Configuration Mismatch Reset has occurred (must be subsequently set in software)
bit 4
RI: RESET
Instruction Flag bit
For details of bit operation, see
.
bit 3
TO:
Watchdog Timer Time-out Flag bit
For details of bit operation, see
.
bit 2
PD:
Power-Down Detection Flag bit
For details of bit operation, see
.
bit 1
POR:
Power-on Reset Status bit
For details of bit operation, see
.
bit 0
BOR:
Brown-out Reset Status bit
For details of bit operation, see
.