Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
2009-2011 Microchip Technology Inc.
DS39960D-page 189
PIC18F87K22 FAMILY
12.11 Parallel Slave Port
PORTD can function as an 8-bit-wide Parallel Slave
Port (PSP), or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. The port is asyn-
chronously readable and writable by the external world
through the RD control input pin (RE0/P2D/RD/AD8)
and WR control input pin (RE1/P2C/WR/AD9).
Port (PSP), or microprocessor port, when control bit,
PSPMODE (PSPCON<4>), is set. The port is asyn-
chronously readable and writable by the external world
through the RD control input pin (RE0/P2D/RD/AD8)
and WR control input pin (RE1/P2C/WR/AD9).
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an eight-bit latch.
Setting bit, PSPMODE, enables port pin,
RE0/P2D/RD/AD8, to be the RD input,
RE1/P2C/WR/AD9 to be the WR input and
RE2/P2B/CCP10/CS/AD10 to be the CS (Chip Select)
input. For this functionality, the corresponding data
direction bits of the TRISE register (TRISE<2:0>) must
be configured as inputs (= 111).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits (PIR1<7>
and PSPCON<7>, respectively) are set when the write
ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit (PSPCON<6>) is set. If the user
writes new data to PORTD to set OBF, the data is
immediately read out, but the OBF bit is not set.
When either the CS or RD line is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in
processor data bus. The external microprocessor can
read or write the PORTD latch as an eight-bit latch.
Setting bit, PSPMODE, enables port pin,
RE0/P2D/RD/AD8, to be the RD input,
RE1/P2C/WR/AD9 to be the WR input and
RE2/P2B/CCP10/CS/AD10 to be the CS (Chip Select)
input. For this functionality, the corresponding data
direction bits of the TRISE register (TRISE<2:0>) must
be configured as inputs (= 111).
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits (PIR1<7>
and PSPCON<7>, respectively) are set when the write
ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit (PSPCON<6>) is set. If the user
writes new data to PORTD to set OBF, the data is
immediately read out, but the OBF bit is not set.
When either the CS or RD line is detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP. When this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in
and
respectively.
FIGURE 12-3:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Note:
The Parallel Slave Port is available only in
Microcontroller mode.
Microcontroller mode.
Data Bus
WR LATD
RDx
Q
D
CK
EN
Q
D
EN
RD PORTD
Pin
(1)
One Bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note:
The I/O pin has protection diodes to V
DD
and V
SS
.
TTL
TTL
TTL
TTL
or
PORTD
RD LATD
Data Latch
TRIS Latch