Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
PIC18F87K22 FAMILY
DS39960D-page 252
2009-2011 Microchip Technology Inc.
19.3
Compare Mode
In Compare mode, the 16-bit CCPR4 register value is
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the CCP4 pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
constantly compared against the Timer register pair
value selected in the CCPTMR1 register. When a
match occurs, the CCP4 pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
latch)
The action on the pin is based on the value of the mode
select bits (CCP4M<3:0>). At the same time, the
interrupt flag bit, CCP4IF, is set.
select bits (CCP4M<3:0>). At the same time, the
interrupt flag bit, CCP4IF, is set.
19.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
clearing the appropriate TRIS bit.
19.3.2
TIMER1/3/5/7 MODE SELECTION
If the CCP module is using the compare feature in
conjunction with any of the Timer1/3/5/7 timers, the
timers must be running in Timer mode or Synchronized
Counter mode. In Asynchronous Counter mode, the
compare operation may not work.
conjunction with any of the Timer1/3/5/7 timers, the
timers must be running in Timer mode or Synchronized
Counter mode. In Asynchronous Counter mode, the
compare operation may not work.
19.3.3
SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP4M<3:0> = 1010), the CCP4 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP4IE bit is set.
(CCP4M<3:0> = 1010), the CCP4 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP4IE bit is set.
19.3.4
SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP4M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
Period register for either timer.
The Special Event Trigger for CCP4 cannot start an
A/D conversion.
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP4M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
Period register for either timer.
The Special Event Trigger for CCP4 cannot start an
A/D conversion.
Note:
Clearing the CCP4CON register will force
the RC1 or RE7 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTC or
PORTE I/O data latch.
the RC1 or RE7 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTC or
PORTE I/O data latch.
Note:
and
Note:
The Special Event Trigger of ECCP2 can start
an A/D conversion, but the A/D Converter
must be enabled. For more information, see
an A/D conversion, but the A/D Converter
must be enabled. For more information, see