Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
2009-2011 Microchip Technology Inc.
DS39960D-page 305
PIC18F87K22 FAMILY
FIGURE 21-13:
I
2
C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SD
A
x
SC
L
x
S
S
P
xIF
(
P
IR1
<
3>
o
r P
IR3<
7
>
)
BF
(
S
SP
xS
TA
T
<
0
>
)
S
1
2
34
5
6
78
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
7
8
9
P
1
1
1
1
0
A
9A
8
A
7
A
6
A
5
A
4A
3A
2
A
1
A
0
1
1
1
1
0
A
8
R/W
=
1
AC
K
AC
K
R/W
=
0
ACK
R
eceive F
ir
st B
yte of
A
d
dr
ess
Cle
a
re
d
in
so
ftwa
re
B
u
s m
aster
term
inates
tran
sfer
A9
6
R
e
ce
iv
e S
econd B
yte
of A
ddre
ss
C
lear
ed by
hard
w
a
re w
hen
SS
PxADD is u
p
d
ate
d
with
lo
w
byte
of ad
dress
U
A
(
S
SPxS
TA
T
<1
>)
Clo
ck is h
e
ld
lo
w u
ntil
up
date o
f S
S
P
xA
D
D
has
ta
ken
pl
ace
UA
is se
t indicatin
g
that
the S
S
P
xA
D
D
nee
ds to b
e
upda
ted
UA
is set
indicating
that
S
S
P
xA
D
D
ne
eds to b
e
up
d
a
te
d
Cle
ar
e
d
b
y h
a
rd
wa
re
wh
e
n
SSP
xADD is u
p
da
te
d
with
h
ig
h
by
te
o
f ad
d
res
s.
SS
PxBUF
is wr
itte
n
with
cont
ent
s of S
S
P
xS
R
D
u
mm
y re
ad of S
S
P
xB
U
F
to cle
a
r B
F
fl
ag
Receive F
irst B
yte
of A
d
dre
ss
12
3
4
5
7
8
9
D
7
D6
D5
D4
D3
D
1
AC
K
D2
6
T
ran
smitting D
ata
B
yt
e
D0
D
u
mm
y re
ad of
S
S
P
xB
U
F
to cle
a
r B
F
fl
ag
Sr
Cle
ar
e
d
in
so
ftwa
re
W
rit
e o
f SS
Px
BUF
in
itia
te
s tr
an
sm
it
C
lea
re
d i
n
s
o
ftw
a
re
Co
m
p
le
tio
n
o
f
clear
s B
F
flag
C
KP (
SSP
xC
O
N
1
<
4
>
)
CKP is se
t in
so
ftwa
re
CK
P is a
u
to
m
a
tica
lly
cl
ea
re
d in
h
a
rd
wa
re
, h
o
ld
in
g
SC
Lx
lo
w
Clo
ck is h
e
ld
lo
w u
n
til
upd
a
te of
S
S
P
xA
D
D
ha
s
ta
ken p
lace
da
ta
tran
smission
Clo
ck is h
e
ld
lo
w u
ntil
CK
P
is set to
‘1
’
th
ir
d ad
dress s
equen
ce
B
F
fl
ag
is clear
at
the e
nd of t
h
e