Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
2009-2011 Microchip Technology Inc.
DS39960D-page 405
PIC18F87K22 FAMILY
REGISTER 28-1:
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
U-0
R/P-1
U-0
R/P-1
R/P-1
R/P-1
U-0
R/P-1
—
XINST
—
SOSCSEL1 SOSCSEL0 INTOSCSEL
—
RETEN
bit 7
bit 0
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented:
Read as ‘0’
bit 6
XINST:
Extended Instruction Set Enable bit
1
= Instruction set extension and Indexed Addressing mode are enabled
0
= Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)
bit 5
Unimplemented:
Read as ‘0’
bit 4-3
SOSCSEL<1:0>:
SOSC Power Selection and Mode Configuration bits
11
= High-power SOSC circuit is selected
10
= Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled
01
= Low-power SOSC circuit is selected
00
= Reserved
bit 2
INTOSCSEL:
LF-INTOSC Low-power Enable bit
1
= LF-INTOSC is in High-Power mode during Sleep
0
= LF-INTOSC is in Low-Power mode during Sleep
bit 1
Unimplemented:
Read as ‘0’
bit 0
RETEN:
V
REG
Sleep Enable bit
1
= Regulator power while in Sleep mode is controlled by VREGSLP (WDTCON<7>)
0
= Regulator power while in Sleep mode is controlled by SRETEN (WDTCON<4>). Ultra low-power
regulator is enabled.