Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
2009-2011 Microchip Technology Inc.
DS39960D-page 57
PIC18F87K22 FAMILY
4.0
POWER-MANAGED MODES
The PIC18F87K22 family of devices offers a total of
seven operating modes for more efficient power man-
agement. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (such as battery-powered
devices).
There are three categories of power-managed mode:
• Run modes
• Idle modes
• Sleep mode
There is an Ultra Low-Power Wake-up (ULPWU) for
waking from the Sleep mode.
These categories define which portions of the device
are clocked, and sometimes, at what speed. The Run
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator
block). The Sleep mode does not use a clock source.
The ULPWU mode, on the RA0 pin, enables a slow fall-
ing voltage to generate a wake-up, even from Sleep,
without excess current consumption. (See
seven operating modes for more efficient power man-
agement. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (such as battery-powered
devices).
There are three categories of power-managed mode:
• Run modes
• Idle modes
• Sleep mode
There is an Ultra Low-Power Wake-up (ULPWU) for
waking from the Sleep mode.
These categories define which portions of the device
are clocked, and sometimes, at what speed. The Run
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator
block). The Sleep mode does not use a clock source.
The ULPWU mode, on the RA0 pin, enables a slow fall-
ing voltage to generate a wake-up, even from Sleep,
without excess current consumption. (See
The power-managed modes include several power-
saving features offered on previous PIC
saving features offered on previous PIC
®
devices. One
is the clock switching feature, offered in other PIC18
devices. This feature allows the controller to use the
SOSC oscillator instead of the primary one. Another
power-saving feature is Sleep mode, offered by all PIC
devices, where all device clocks are stopped.
devices. This feature allows the controller to use the
SOSC oscillator instead of the primary one. Another
power-saving feature is Sleep mode, offered by all PIC
devices, where all device clocks are stopped.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
• Will the CPU be clocked or not
• What will be the clock source
decisions:
• Will the CPU be clocked or not
• What will be the clock source
The IDLEN bit (OSCCON<7>) controls CPU clocking,
while the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
while the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
.
4.1.1
CLOCK SOURCES
The SCS<1:0> bits select one of three clock sources
for power-managed modes. Those sources are:
• The primary clock as defined by the FOSC<3:0>
for power-managed modes. Those sources are:
• The primary clock as defined by the FOSC<3:0>
Configuration bits
• The secondary clock (the SOSC oscillator)
• The internal oscillator block (for LF-INTOSC
• The internal oscillator block (for LF-INTOSC
modes)
4.1.2
ENTERING POWER-MANAGED
MODES
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is used. Changing these bits
causes an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These considerations
are discussed in
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is used. Changing these bits
causes an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These considerations
are discussed in
Entering the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current and impending mode, a
change to a power-managed mode does not always
require setting all of the previously discussed bits. Many
transitions can be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
desired, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current and impending mode, a
change to a power-managed mode does not always
require setting all of the previously discussed bits. Many
transitions can be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
desired, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 4-1:
POWER-MANAGED MODES
Mode
OSCCON Bits
Module Clocking
Available Clock and Oscillator Source
IDLEN<7>
(
)
SCS<1:0>
CPU
Peripherals
Sleep
0
N/A
Off
Off
None – All clocks are disabled
PRI_RUN
N/A
00
Clocked
Clocked
Primary – XT, LP, HS, EC, RC and PLL modes.
This is the normal, Full-Power Execution mode.
This is the normal, Full-Power Execution mode.
SEC_RUN
N/A
01
Clocked
Clocked
Secondary – SOSC Oscillator
RC_RUN
N/A
1x
Clocked
Clocked
Internal oscillator block
PRI_IDLE
1
00
Off
Clocked
Primary – LP, XT, HS, RC, EC
SEC_IDLE
1
01
Off
Clocked
Secondary – SOSC oscillator
RC_IDLE
1
1x
Off
Clocked
Internal oscillator block
Note 1:
IDLEN reflects its value when the SLEEP instruction is executed.
2:
Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC
source.
source.