Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
PIC18F87K22 FAMILY
DS39960D-page 60
2009-2011 Microchip Technology Inc.
4.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the LF-INTOSC source, this
mode provides the best power conservation of all the
Run modes, while still executing code. It works well for
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block – either LF-INTOSC or INTOSC (MF-INTOSC or
HF-INTOSC) – there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. Entering or exiting RC_RUN mode, how-
ever, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it is
recommended that the SCS0 bit also be cleared, even
though the bit is ignored. When the clock source is
switched to the INTOSC multiplexer (see
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the LF-INTOSC source, this
mode provides the best power conservation of all the
Run modes, while still executing code. It works well for
user applications which are not highly timing-sensitive
or do not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block – either LF-INTOSC or INTOSC (MF-INTOSC or
HF-INTOSC) – there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. Entering or exiting RC_RUN mode, how-
ever, causes a clock switch delay. Therefore, if the
primary clock source is the internal oscillator block,
using RC_RUN mode is not recommended.
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it is
recommended that the SCS0 bit also be cleared, even
though the bit is ignored. When the clock source is
switched to the INTOSC multiplexer (see
),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
.
TABLE 4-3:
INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
Note:
Caution should be used when modifying a
single IRCF bit. At a lower V
single IRCF bit. At a lower V
DD
, it is
possible to select a higher clock speed
than is supportable by that V
than is supportable by that V
DD
. Improper
device operation may result if the V
DD
/
F
OSC
specifications are violated.
IRCF<2:0>
INTSRC
MFIOSEL
Status of MFIOFS or HFIOFS when INTOSC is Stable
000
0
x
MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC
000
1
0
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
000
1
1
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Non-Zero
x
0
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
Non-Zero
x
1
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC