Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Data Sheet
Product codes
PIC18F65K22-I/PT
2009-2011 Microchip Technology Inc.
DS39960D-page 73
PIC18F87K22 FAMILY
5.0
RESET
The PIC18F87K22 family of devices differentiates
between various kinds of Reset:
a)
between various kinds of Reset:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during power-managed modes
d)
Watchdog Timer (WDT) Reset (during
execution)
execution)
e)
Configuration Mismatch (CM) Reset
f)
Brown-out Reset (BOR)
g)
RESET
Instruction
h)
Stack Full Reset
i)
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”
WDT Resets are covered in
.
A simplified block diagram of the on-chip Reset circuit
is shown in
is shown in
5.1
RCON Register
Device Reset events are tracked through the RCON
register (
register (
). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event.
The state of these flag bits, taken together, can be read
to indicate the type of Reset that just occurred. This is
described in more detail in
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event.
The state of these flag bits, taken together, can be read
to indicate the type of Reset that just occurred. This is
described in more detail in
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in
interrupt priority (IPEN). Interrupt priority is discussed
in
.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
V
DD
WDT
Time-out
V
DD
Rise
Detect
PWRT
LF-INTOSC
POR Pulse
Chip_Reset
Brown-out
Reset
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
32
s
PWRT
11-Bit Ripple Counter
66 ms
S
R
Q
Configuration Word Mismatch