Microchip Technology XC8 Standard Compiler (Workstation) SW006021-1 SW006021-1 User Manual
Product codes
SW006021-1
MPLAB
®
XC8 C Compiler User’s Guide
DS52053B-page 248
2012 Microchip Technology Inc.
6.4.1.4
LONG JUMPS AND CALLS
The assembler recognizes several mnemonics which expand into regular PIC MCU
assembly instructions. The mnemonics are FCALL and LJMP. On baseline and
mid-range parts, these instructions expand into regular CALL and GOTO instructions
respectively, but also ensure the instructions necessary to set the bits in PCLATH (for
mid-range devices) or STATUS (for baseline devices) will be generated when the des-
tination is in another page of program memory.Whether the page selection instructions
are generated, and exactly where they will be located, is dependent on the surrounding
source code. Page selection instructions may appear immediately before the call or
jump, or be generated as part of, and immediately after, a previous FCALL/LJMP
instruction.
assembly instructions. The mnemonics are FCALL and LJMP. On baseline and
mid-range parts, these instructions expand into regular CALL and GOTO instructions
respectively, but also ensure the instructions necessary to set the bits in PCLATH (for
mid-range devices) or STATUS (for baseline devices) will be generated when the des-
tination is in another page of program memory.Whether the page selection instructions
are generated, and exactly where they will be located, is dependent on the surrounding
source code. Page selection instructions may appear immediately before the call or
jump, or be generated as part of, and immediately after, a previous FCALL/LJMP
instruction.
On PIC18 devices, these mnemonics are present purely for compatibility with smaller
8-bit devices and are always expanded as regular PIC18 CALL and GOTO instructions.
8-bit devices and are always expanded as regular PIC18 CALL and GOTO instructions.
These additional mnemonics should be used where possible as they make assembly
code independent of the final position of the routines that are to be executed. If the call
or jump is determined to be within the current page, the additional code to set the
PCLATH
code independent of the final position of the routines that are to be executed. If the call
or jump is determined to be within the current page, the additional code to set the
PCLATH
bits may be optimized away. Note that assembly code that is added in-line with
C code is never optimized and assembly modules require a specific option to enable
optimization, see Section 4.8.42 “--OPT: Invoke Compiler Optimizations”. Unopti-
mized FCALL and LJMP instruction will always generate page selection code.
optimization, see Section 4.8.42 “--OPT: Invoke Compiler Optimizations”. Unopti-
mized FCALL and LJMP instruction will always generate page selection code.
The following mid-range PIC example shows an FCALL instruction in the assembly list
file. You can see that the FCALL instruction has expanded to five instructions. In this
example there are two bit instructions which set/clear bits in the PCLATH register. Bits
are also set/cleared in this register after the call to reselect the page which was
selected before the FCALL.
file. You can see that the FCALL instruction has expanded to five instructions. In this
example there are two bit instructions which set/clear bits in the PCLATH register. Bits
are also set/cleared in this register after the call to reselect the page which was
selected before the FCALL.
13 0079 3021 movlw 33
14 007A 120A 158A 2000 fcall _phantom
120A 118A
15 007F 3400 retlw 0
Since FCALL and LJMP instructions may expand into more than one instruction, they
should never be preceded by an instruction that can skip, e.g., a BTFSC instruction.
should never be preceded by an instruction that can skip, e.g., a BTFSC instruction.
On PIC18 devices, the regular CALL instruction may be followed by a ",f" to indicate
that the W, STATUS and BSR registers should be pushed to their respective shadow
registers. This replaces the ",1" syntax indicated on the device data sheet.
that the W, STATUS and BSR registers should be pushed to their respective shadow
registers. This replaces the ",1" syntax indicated on the device data sheet.
6.4.1.5
RELATIVE BRANCHES
The PIC18 devices implement conditional relative branch instructions, e.g., BZ, BNZ.
These instructions have a limited jump range compared to the GOTO instruction.
These instructions have a limited jump range compared to the GOTO instruction.
Note that in some instance, the assembler may change a relative branch instruction to
be a relative branch with the opposite condition over a GOTO instruction. For example:
be a relative branch with the opposite condition over a GOTO instruction. For example:
BZ error
;next
may become:
BNZ l18
GOTO error
l18:
;next
This is functionally identical and is performed so that the conditional branch can use
the same destination range as the GOTO instruction.
the same destination range as the GOTO instruction.