Texas Instruments LMK01000 Evaluation Board LMK01000EVAL/NOPB LMK01000EVAL/NOPB Data Sheet
![Texas Instruments](https://files.manualsbrain.com/attachments/b46f99d826b2b0e0e5f558c5fb6483942eb9216b/common/fit/150/50/c15ea36eb1fb1cce99a3b94668675bfc78ce832d8d727d9a7bb51a125510/brand_logo.gif)
Product codes
LMK01000EVAL/NOPB
SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009
Package Thermal Resistance
Package
θ
JA
θ
J-PAD (Thermal Pad)
48-Lead LLP
(1)
27.4° C/W
5.8° C/W
(1)
Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These
vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in
the board layout.
vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in
the board layout.
Copyright © 2008–2009, Texas Instruments Incorporated
5
Product Folder Links: