Intel Celeron Processors 540 BX80537540 Data Sheet

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the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the 
Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of 

specification and may result in unapproved operation. 

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will 

cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching 
interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or 

RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input 

signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in 
the RESET# pin specification, then the processor will reset itself, ignoring the transition through 

Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# 

and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the 
processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power state, the Deep 

Sleep state by asserting the DPSLP# pin. (see 

.). While the processor is in the Sleep 

state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur. 

Deep Sleep state is a very low-power state the processor can enter while maintaining context. Deep 

Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped 
during the Deep Sleep state for additional platform-level power savings. BCLK stop/restart timings 

on Intel 855PM/ICH4-M, Intel 855GM/ICH4-M, and Intel 852GM/ICH4-M chipset-based 

platforms with the CK-408 clock chip are as follows:

•

Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. CK-408 will stop/

tristate BCLK within 2 BCLKs +/- a few nanoseconds.

•

Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. CK-408 will drive 
BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6 BCLK periods 

later.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after 
DPSLP# deassertion as described above. A period of 30 microseconds (to allow for PLL 

stabilization) must occur before the processor can be considered to be in the Sleep State. Once in 

the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop transactions or 
latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in 

Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant 

state will result in unpredictable behavior.

When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. 

The Intel Celeron M processor incorporates the following FSB low power enhancements:

•

Dynamic FSB power-down