Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Data Sheet
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Product codes
DK-TM4C129X
In addition, the following bits control both BOR events:
■
BORIM
bit in the Interrupt Mask Control (IMC) register, System Control offset 0x054.
■
VDDA_UBOR0
and
VDD_UBOR0
bits in the Power-Temperature Cause (PWRTC) register.
Please refer to “System Control” on page 230 for more information on how to configure these
registers.
registers.
Figure 32-5 on page 2110 shows the relationship between V
DD
, POK, POR and a BOR event.
Figure 32-5. Power and Brown-Out Assertions vs V
DD
Levels
P2
VDD
P7
RISE
P8
POK
VDD
MIN
1
0
P7
FALL
BOR
1
0
32.6.3
V
DDC
Levels
The V
DDC
supply has one monitor, the Power-OK (POK). The POK monitor is used to keep the
digital circuitry in reset until the V
DDC
power supply is at an acceptable operational level. The digital
reset is only released when the Power-On Reset has deasserted and all of the Power-OK monitors
for each of the supplies indicate that power levels are in operational ranges. Figure 32-6 on page 2111
shows the relationship between POK and V
for each of the supplies indicate that power levels are in operational ranges. Figure 32-6 on page 2111
shows the relationship between POK and V
DDC
.
December 13, 2013
2110
Texas Instruments-Advance Information
Electrical Characteristics