Texas Instruments 0A Evaluation Module Featuring the TPS51117 Synchronous Buck Controller with D-CAP Mode TPS51117EVM TPS51117EVM Data Sheet
Product codes
TPS51117EVM
I
G
+
Qg
ƒ
sw
W
DRIVE
+
V
V5DRV
ǒ
Q
g(top)
)
Q
g(btm)
Ǔ
ƒ
sw
W
PKG
+
T
J(max)
*
T
A(max)
q
JA
www.ti.com
......................................................................................................................................
SLVS631B – DECEMBER 2005 – REVISED SEPTEMBER 2009
Apply 0.1-
μ
F MLCC between VBST and the LL node as the flying capacitor for the high-side FET driver. The
TPS51117 has its own boost diode on-board between V5DRV and VBST. This is a PN junction diode and
strong enough for most typical applications. However, in case efficiency has priority over cost, the designer
may add a Schottky diode externally to improve gate drive voltage of the high-side FET. A Schottky diode
has a higher leakage current, especially at high temperature, than a PN junction diode. A low leakage diode
should be selected in order to maintain VBST voltage during low frequency operation in skip mode.
strong enough for most typical applications. However, in case efficiency has priority over cost, the designer
may add a Schottky diode externally to improve gate drive voltage of the high-side FET. A Schottky diode
has a higher leakage current, especially at high temperature, than a PN junction diode. A low leakage diode
should be selected in order to maintain VBST voltage during low frequency operation in skip mode.
THERMAL CONSIDERATION
Power dissipation of the TPS51117 is mainly generated from the FET drivers. Average drive current can be
estimated by gate charge, Q
estimated by gate charge, Q
g
, times the switching frequency.
(14)
Q
g
is the charge needed to charge gate capacitance up to the V5DRV voltage of 5 V. Actual values are shown
on MOSFET datasheets provided by the manufacturer. Total power dissipation, therefore, to drive the top and
bottom MOSFETs can be calculated by the following equation
bottom MOSFETs can be calculated by the following equation
(15)
This power plus a small amount of dissipation (less than 5 mW) from controller circuitry needs to be effectively
dissipated from the package. Maximum power dissipation allowed for the package is calculated by:
dissipated from the package. Maximum power dissipation allowed for the package is calculated by:
(16)
Where
•
•
T
J(max)
is 125°C
•
T
A(max)
is the maximum ambient temperature in the system
•
θ
JA
is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on board layout. The TPS51117 is assembled in a standard TSSOP
package and the heat mainly moves to the board through its leads.
package and the heat mainly moves to the board through its leads.
LAYOUT CONSIDERATIONS
Certain points must be considered before starting a layout work using the TPS51117.
•
•
Connect the RC low-pass filter from 5-V supply to V5FILT, 300
Ω
and 1
μ
F are recommended. Place the filter
capacitor close to the device, within 12 mm (0.5 inches) if possible.
•
Connect the overcurrent setting resistors from TRIP to GND close to the device, right next to the device, if
possible. The trace from TRIP to resistor and resistor to GND should avoid coupling to a high voltage
switching node.
possible. The trace from TRIP to resistor and resistor to GND should avoid coupling to a high voltage
switching node.
•
The discharge path (VOUT) should have a dedicated trace to the output capacitor(s); separate from the
output voltage sensing trace, and use a 1,5 mm (60 mils) or wider trace with no loops. Make sure the
feedback current setting resistor (the resistor between VFB to GND) is tied close to the device GND. The
trace from this resistor to the VFB pin should be short and thin. Place on the component side and avoid vias
between this resistor and the device.
output voltage sensing trace, and use a 1,5 mm (60 mils) or wider trace with no loops. Make sure the
feedback current setting resistor (the resistor between VFB to GND) is tied close to the device GND. The
trace from this resistor to the VFB pin should be short and thin. Place on the component side and avoid vias
between this resistor and the device.
•
Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use a 0.65 mm (25 mils) or wider trace.
short as possible to reduce stray inductance. Use a 0.65 mm (25 mils) or wider trace.
•
All sensitive analog traces and components such as VOUT, VFB, GND, EN_PSV, PGOOD, TRIP, V5FILT,
and TON should be placed away from high-voltage switching nodes such as LL, DRVL, DRVH or VBST to
avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and
components.
and TON should be placed away from high-voltage switching nodes such as LL, DRVL, DRVH or VBST to
avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and
components.
•
Gather the ground terminals of the V
IN
capacitor(s), V
OUT
capacitor(s), and the source of the low-side
MOSFETs as close as possible. GND (signal ground) and PGND (power ground) should be connected
strongly together near the device. The PCB trace defined as LL node, which connects to the source of the
high-side MOSFET, the drain of the low-side MOSFET, and the high-voltage side of the inductor, should be
as short and wide as possible.
strongly together near the device. The PCB trace defined as LL node, which connects to the source of the
high-side MOSFET, the drain of the low-side MOSFET, and the high-voltage side of the inductor, should be
as short and wide as possible.
Copyright © 2005–2009, Texas Instruments Incorporated
19
Product Folder Link(s) :