Texas Instruments 0A Evaluation Module Featuring the TPS51117 Synchronous Buck Controller with D-CAP Mode TPS51117EVM TPS51117EVM Data Sheet
Product codes
TPS51117EVM
2.9
3.9 /3.6
48
SLVS631B – DECEMBER 2005 – REVISED SEPTEMBER 2009
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FUNCTIONAL BLOCK DIAGRAM
DETAILED DESCRIPTION
PWM OPERATION
The main control loop of the TPS51117 is designed as an adaptive on-time pulse width modulation (PWM)
controller. It supports proprietary D-CAP™ Mode that uses an internal compensation circuit and is suitable for
minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is
allowed. Basic operation of D-CAP Mode can be described as follows.
controller. It supports proprietary D-CAP™ Mode that uses an internal compensation circuit and is suitable for
minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is
allowed. Basic operation of D-CAP Mode can be described as follows.
6
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