Texas Instruments FPD Link III - DS90UB903Q & DS90UB904Q EVK SERDESUB-21USB/NOPB SERDESUB-21USB/NOPB Data Sheet

 

7 

SNLU101 – April 2012 

 

 

The 2x22-pin IDC connector J1 accepts 21 bits of 1.8V or 3.3V data along with the PCLK 
clock input.  VDDIO must be set externally for 1.8V or 3.3V LVCMOS inputs. 
 
The Serializer board is powered externally from the J5 (VDD) and J6 (VSS) connectors 
shown below.  For the Serializer to be operational, the S1-PDB switch on S1 must be set 
HIGH. S1-RES0 must be set LOW.  Master or slave mode is user selected on S1-M_S 
(MODE). please refer to DS90UB903/904 datasheet for details. 
 
The USB connector P2 (USB-A side) on the bottom side of the board provides the 
interface connection to the Deserializer board.  Note: P3 (mini USB) on the top side is un-
stuffed and not to be used with the cable provided in the kit. 
 
   

 

 

Note: 
1) VDD and VSS MUST be 
applied externally from 
here. 
2) VDDIO = 3.3V should 
be applied separately on 
JP12 with default jumper 
on JP11 (VDDI=+3.3V), 
otherwise jumper VDDIO 
to +1.8V 

c

 P2 (BACKSIDE)

 

f

 

J5, J6 

JP12  

c

 

FPD-LINK III I/O

  

d

 LVCMOS INPUTS 

e

 

FUNCTION CONTROLS  

 

f

 

POWER SUPPLY

 

g

 

INPUT TERMINATION 

Ω

Ω

h

 

I2C BUS CONTROL  

i

 

GPO 

J1 

d

 

S1 

e

 

g

 

g

 

g

 

g

 

c

 P3 (TOPSIDE) 

   (UNSTUFFED) 

Note: 
Connect cable 
(USB A side) 
to P2 on BACKSIDE.

J4,JP8,JP9 

h

 

JP1 to JP4  

i