Microchip Technology 24LC02BT-I/LT Memory IC SC-70-5 24LC02BT-I/LT Data Sheet

DS21709J-page 10

© 2009 Microchip Technology Inc.

Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘

1

’. There are three basic types

of read operations: current address read, random read
and sequential read.

The 24XX02 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘

1

’. Therefore, if the previous access

(either a read or write operation) was to address 

n

, the

next current address read operation would access data
from address 

n + 1

. Upon receipt of the slave address

with R/W bit set to ‘

1

’, the 24XX02 issues an acknowl-

edge and transmits the 8-bit data word. The master will
not acknowledge the transfer, but does generate a Stop
condition, and the 24XX02 discontinues transmission
(Figure 8-1).

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX02 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘

1

’. The

24XX02 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition, and
the 24XX02 will discontinue transmission (Figure 8-2).

Sequential reads are initiated in the same way as a
random read, except that once the 24XX02 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX02 to transmit the next sequentially-
addressed 8-bit word (Figure 8-3).

To provide sequential reads, the 24XX02 contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.

The 24XX02 employs a V

CC

 threshold detector circuit

which disables the internal erase/write logic if the V

CC

is below 1.5V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.

S

P

Bus Activity
Master

SDA Line

Bus Activity

S
T
O
P

Control

Byte

Data (n)

A
C
K

N
o
 
A
C
K

S
T
A
R
T

1

0

1

0

x

x

x

1

Block

Select

Bits

x

 = “don’t care”