Microchip Technology 24LC02BT-I/LT Memory IC SC-70-5 24LC02BT-I/LT Data Sheet
Product codes
24LC02BT-I/LT
© 2009 Microchip Technology Inc.
DS21709J-page 3
24AA02/24LC02B
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E):
T
A
= -40°C to +125°C,V
CC
= +2.5V to +5.5V
Param.
No.
Sym.
Characteristic
Min.
Typ.
Max.
Units
Conditions
1
F
CLK
Clock frequency
—
—
—
—
—
—
400
100
100
kHz
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
2
T
HIGH
Clock high time
600
4000
—
—
—
—
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
3
T
LOW
Clock low time
1300
4700
4700
—
—
—
—
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
4
T
R
SDA and SCL rise time
(Note 1)
(Note 1)
—
—
—
—
—
—
300
1000
ns
2.5V
≤ V
CC
≤ 5.5V (Note 1)
1.7V
≤ V
CC
< 2.5V (24AA02)
5
T
F
SDA and SCL fall time
—
—
—
—
300
ns
6
T
HD
:
STA
Start condition hold time
600
4000
—
—
—
—
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
7
T
SU
:
STA
Start condition setup
time
time
600
4700
—
—
—
—
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
8
T
HD
:
DAT
Data input hold time
0
—
—
—
—
ns
9
T
SU
:
DAT
Data input setup time
100
250
250
—
—
—
—
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
10
T
SU
:
STO
Stop condition setup
time
time
600
4000
—
—
—
—
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
11
T
AA
Output valid from clock
(Note 2)
(Note 2)
—
—
—
—
—
—
900
3500
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
12
T
BUF
Bus free time: Time the
bus must be free before
a new transmission can
start
bus must be free before
a new transmission can
start
1300
4700
4700
—
—
—
—
—
—
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
13
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
20+0.1C
B
—
—
—
—
250
250
250
ns
2.5V
≤ V
CC
≤ 5.5V
1.7V
≤ V
CC
< 2.5V (24AA02)
14
T
SP
Input filter spike
suppression
(SDA and SCL pins)
suppression
(SDA and SCL pins)
—
—
50
ns
(Notes 1 and 3)
15
T
WC
Write cycle time (byte or
page)
page)
—
—
5
ms
—
16
—
Endurance
1M
—
—
cycles
25°C, (Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a
T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.