STMicroelectronics M24C64-WBN6P Memory IC M24C64-WBN6P Data Sheet
Product codes
M24C64-WBN6P
DocID16891 Rev 28
M24C64-W M24C64-R M24C64-F
41
5.1.1 Byte
Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in
.
Figure 8. Write mode sequences with WC = 0 (data write enabled)
Stop
Start
Byte Write
Dev sel
Byte addr
Byte addr
Data in
WC
Start
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
WC
Data in 2
AI01106d
Page Write (cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK
ACK
ACK
ACK
ACK
ACK
ACK
R/W
ACK
ACK