Microchip Technology MCP6V01RD-TCPL Data Sheet

© 2008 Microchip Technology Inc.

DS22058C-page 19

Descriptions of the pins are listed in 

.

The analog output pins (V

OUT

) are low-impedance

voltage sources.

The non-inverting and inverting inputs (V

IN

+, V

IN

–, …)

are high-impedance CMOS inputs with low bias
currents.

The positive power supply (V

DD

) is 1.8V to 5.5V higher

than the negative power supply (V

SS

). For normal

operation, the other pins are between V

SS

 and V

DD

.

Typically, these parts are used in a single (positive)
supply configuration. In this case, V

SS

 is connected to

ground and V

DD

 is connected to the supply. V

DD

 will

need bypass capacitors.

This pin (CS) is a CMOS, Schmitt-triggered input that
places the MCP6V03 op amps into a low power mode
of operation.

There is an internal connection between the Exposed
Thermal Pad (EP) and the V

SS

 pin; they must be con-

nected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (

θ

JA

).

TDFN

SOIC

DFN

SOIC

TDFN

SOIC

6

6

1

1

6

6

V

OUT

, V

OUTA

Output (op amp A)

2

2

2

2

2

2

V

IN

–, V

INA

–

Inverting Input (op amp A)

3

3

3

3

3

3

V

IN

+, V

INA

+

Non-inverting Input
(op amp A)

4

4

4

4

4

4

V

SS

Negative Power Supply

—

—

5

5

—

—

V

INB

+

Non-inverting Input
(op amp B)

—

—

6

6

—

—

V

INB

–

Inverting Input (op amp B)

—

—

7

7

—

—

V

OUTB

Output (op amp B)

7

7

8

8

7

7

V

DD

Positive Power Supply

—

—

—

—

—

8

CS

Chip Select (op amp A)

1, 5, 8

1, 5, 8

—

—

1, 5, 8

1, 5

NC

No Internal Connection

9

—

9

—

9

—

EP

Exposed Thermal Pad (EP); 
must be connected to V

SS