Microchip Technology DM164130-9 User Manual
PICkit™ 3 Starter Kit User’s Guide
DS41628B-page 56
2012 Microchip Technology Inc.
The PIC18F14K22 has a slightly different ANSEL register, but the functionality is the
same. The top row of each register screen shot in every PIC microcontroller data sheet
and in this document indicates more information on the functionality of each bit, such
as its default state. The bit ANSA0, is read/writable, and will default to an analog input
same. The top row of each register screen shot in every PIC microcontroller data sheet
and in this document indicates more information on the functionality of each bit, such
as its default state. The bit ANSA0, is read/writable, and will default to an analog input
both on Power-on Reset (POR) and Brown-out Reset (BOR). A BOR will happen if the
supply voltage sags below the threshold determined by the Configuration Words.
supply voltage sags below the threshold determined by the Configuration Words.
3.5.4.1.2
ADCON0
ADCON0 controls the ADC operation. Bit 0 turns on the ADC module. Bit 1 starts a con-
version and bits <6:2> select which channel the ADC will read.
For purposes of this lesson, the ADC must be turned on with RA4 selected as the input
channel. Choose the internal voltage reference and 8T
channel. Choose the internal voltage reference and 8T
OSC
conversion clock. The ADC
needs about 5 μs, after changing channels, to allow the ADC sampling capacitor to set-
tle. Finally, the conversion can be started by setting the GO bit in ADCON0. The GO bit
tle. Finally, the conversion can be started by setting the GO bit in ADCON0. The GO bit
also serves as the DONE flag. That is, the ADC will clear the GO bit in hardware when
the conversion is complete. The result is then available in ADRESH:ADRESL.
The Most Significant four bits of the result are copied and displayed on the LEDs driven
by PORTC.
The Most Significant four bits of the result are copied and displayed on the LEDs driven
by PORTC.
3.5.4.2
PIC16
3.5.4.3
PIC18
3.5.4.3.1
ADCON1:
ADCON1 for the PIC16 and ADCON2 for the PIC18 select the ratio between processor
clock speed and conversion speed. This is important because the ADC needs at least
1.6 μs conversion time per bit. Accuracy degrades if the clock speed is too high or too
slow. As the processor clock speed increases, an increasingly large divider is neces-
sary to maintain the conversion speed.
ADFM bit <7> selects whether the ten result bits are right or left justified. The program
will left justify the result so that the two LSbs are contained in ADRESL and the top eight
in ADRESH. The program, however, will only use the top four MSbs in ADRESH.
The ADNREG/ADPREG bits select the ADC reference, which may be either V
clock speed and conversion speed. This is important because the ADC needs at least
1.6 μs conversion time per bit. Accuracy degrades if the clock speed is too high or too
slow. As the processor clock speed increases, an increasingly large divider is neces-
sary to maintain the conversion speed.
ADFM bit <7> selects whether the ten result bits are right or left justified. The program
will left justify the result so that the two LSbs are contained in ADRESL and the top eight
in ADRESH. The program, however, will only use the top four MSbs in ADRESH.
The ADNREG/ADPREG bits select the ADC reference, which may be either V
DD
or a
separate reference voltage on V
REF
.
TABLE 3-15:
ADC RESULT THAT IS LEFT JUSTIFIED – BITS IN BLUE ARE MIRRORED TO LATC.
BIT 6 REFLECTS DS1, BIT 7 CONTROLS DS2, AND SO FORTH.
BIT 6 REFLECTS DS1, BIT 7 CONTROLS DS2, AND SO FORTH.
Reg
ADRESH
ADRESL
Merged
Bit #
Bit #
10
8
7
6
5
4
3
2
1
(LSb) 0
TABLE 3-16:
NEW REGISTERS FOR ENHANCED MID-RANGE
Register
Purpose
ADCON1
Result format – Speed – Reference voltage
TABLE 3-17:
NEW REGISTERS FOR PIC18
Register
Purpose
ADCON1
Reference voltage
ADCON2
Result format – Speed