Microchip Technology SW006023-2 Data Sheet
MPLAB
®
XC32 C/C++ Compiler User’s Guide
DS51686E-page 154
2012 Microchip Technology Inc.
12.3.5.19 DEBUG2 REGISTER (Debug2 – CP0 REGISTER 23, SELECT 5)
This register holds additional information about complex breakpoint exceptions. The
Debug2
Debug2
register is only implemented if complex hardware breakpoints are present.
No initialization is performed on this register in the PIC32MX start-up code.
12.3.5.20 DEBUG EXCEPTION PROGRAM COUNTER (DEPC – CP0 REGISTER
24, SELECT 0)
This register is a read/write register that contains the address at which processing
resumes after a debug exception or Debug mode exception has been serviced. For
synchronous (precise) debug and Debug mode exceptions, the DEPC contains either:
resumes after a debug exception or Debug mode exception has been serviced. For
synchronous (precise) debug and Debug mode exceptions, the DEPC contains either:
• The virtual address of the instruction that was the direct cause of the debug
exception, or
• The virtual address of the immediately preceding branch or jump instruction, when
the debug exception causing instruction is in a branch delay slot, and the Debug
Branch Delay (DBD) bit in the Debug register is set.
Branch Delay (DBD) bit in the Debug register is set.
For asynchronous debug exceptions (debug interrupt, complex break), the DEPC
contains the virtual address of the instruction where execution should resume after the
debug handler code is executed.
contains the virtual address of the instruction where execution should resume after the
debug handler code is executed.
No initialization is performed on this register in the PIC32MX start-up code.
12.3.5.21 ERROR EXCEPTION PROGRAM COUNTER (ErrorEPC – CP0
REGISTER 30, SELECT 0)
This register is a read/write register, similar to the EPC register, except that it is used on
error exceptions. All bits of the ErrorEPC are significant and must be writable. It is also
used to store the program counter on Reset, Soft Reset, and Non-Maskable Interrupt
(NMI) exceptions. The ErrorEPC register contains the virtual address at which
instruction processing can resume after servicing an error. This address can be:
error exceptions. All bits of the ErrorEPC are significant and must be writable. It is also
used to store the program counter on Reset, Soft Reset, and Non-Maskable Interrupt
(NMI) exceptions. The ErrorEPC register contains the virtual address at which
instruction processing can resume after servicing an error. This address can be:
• The virtual address of the instruction that caused the exception, or
• The virtual address of the immediately preceding branch or jump instruction when
the error causing instruction is a branch delay slot.
Unlike the EPC register, there is no corresponding branch delay slot indication for the
ErrorEPC
ErrorEPC
register.
No initialization is performed on this register in the PIC32MX start-up code.
12.3.5.22 DEBUG EXCEPTION SAVE REGISTER (DeSave – CP0 REGISTER 31,
SELECT 0)
This register is a read/write register that functions as a simple memory location. This
register is used by the debug exception handler to save one of the GPRs that is then
used to save the rest of the context to a pre-determined memory area (such as in the
EJTAG Probe). This register allows the safe debugging of exception handlers and other
types of code where the existence of a valid stack for context saving cannot be
assumed.
register is used by the debug exception handler to save one of the GPRs that is then
used to save the rest of the context to a pre-determined memory area (such as in the
EJTAG Probe). This register allows the safe debugging of exception handlers and other
types of code where the existence of a valid stack for context saving cannot be
assumed.
No initialization is performed on this register in the PIC32MX start-up code.
12.3.6
Call “On Bootstrap” Procedure
A procedure is called after initializing the CP0 registers. This procedure allows users to
perform actions during bootstrap (i.e., while StatusBEV is set) and before entering into
the main routine. An empty weak version of this procedure (_on_bootstrap) is
provided with the start-up code. This procedure may be used for performing hardware
initialization and/or for initializing the environment required by an RTOS.
perform actions during bootstrap (i.e., while StatusBEV is set) and before entering into
the main routine. An empty weak version of this procedure (_on_bootstrap) is
provided with the start-up code. This procedure may be used for performing hardware
initialization and/or for initializing the environment required by an RTOS.