Microchip Technology Microstick for the 3V PIC24F K-series DM240013-1 DM240013-1 Data Sheet

DS39927C-page 126

 2008-2011 Microchip Technology Inc.

The following steps should be taken when configuring
the output compare module for PWM operation:
1.

Set the PWM period by writing to the selected
Timer Period register (PRy).

2.

Set the PWM duty cycle by writing to the OC1RS
register.

3.

Write the OC1R register with the initial duty
cycle.

4.

Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin
utilization.

5.

Configure the output compare module for one of
two PWM Operation modes by writing to the
Output Compare Mode bits, OCM<2:0>
(OC1CON<2:0>).

6.

Set the TMRy prescale value and enable the
time base by setting TON (TxCON<15>) = 1.

15.3.1

 PWM PERIOD

The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using 

.

15.3.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the
OC1RS register. The OC1RS register can be written to
at any time, but the duty cycle value is not latched into
OC1R until a match between PRy and TMRy occurs
(i.e., the period is complete). This provides a double
buffer for the PWM duty cycle and is essential for
glitchless PWM operation. In PWM mode, OC1R is a
read-only register.
Some important boundary parameters of the PWM duty
cycle include:
• If the Output Compare 1 register, OC1R, is loaded 

with 0000h, the OC1 pin will remain low (0% duty 
cycle).

• If OC1R is greater than PRy (Timer Period 

register), the pin will remain high (100% duty 
cycle).

• If OC1R is equal to PRy, the OC1 pin will be low 

for one time base count value and high for all 
other count values.

See 

 for PWM mode timing details.

 provides an example of PWM frequencies

and resolutions for a device operating at 10 MIPS.

The OC1R register should be initialized
before the output compare module is first
enabled. The OC1R register becomes a
read-only Duty Cycle register when the
module is operated in the PWM modes.
The value held in OC1R will become the
PWM duty cycle for the first PWM period.
The contents of the Output Compare 1
Secondary register, OC1RS, will not be
transferred into OC1R until a time base
period match occurs.

A PRy value of N will produce a PWM
period of N + 1 time base count cycles. For
example, a value of 7, written into the PRy
register, will yield a period consisting of
8 time base cycles.

PWM Period = [(PRy) + 1] • T

CY

 • (Timer Prescale Value)

PWM Frequency = 1/[PWM Period]

where:

Based on T

CY

 = 2 * T

OSC

; Doze mode 

and PLL are disabled.

(

 

 )

Maximum PWM Resolution (bits) =

F

CY

 F

PWM

 • (Timer Prescale Value)

log

10

log

10

(2)

bits

Based on F

CY

 = F

OSC

/2; Doze mode and PLL are disabled.