Microchip Technology Microstick for the 3V PIC24F K-series DM240013-1 DM240013-1 Data Sheet

 2008-2011 Microchip Technology Inc.

DS39927C-page 133

To set up the SPI module for the Enhanced Buffer
Master (EBM) mode of operation:
1.

If using interrupts:
a)

Clear the respective SPI1IF bit in the IFS0
register.

b)

Set the respective SPI1IE bit in the IEC0
register.

c)

Write the respective SPI1IPx bits in the
IPC2 register.

2.

Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.

3.

Clear the SPIROV bit (SPI1STAT<6>).

4.

Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).

5.

Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).

6.

Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.

To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.

Clear the SPI1BUF register.

2.

If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0

register.

b) Set the respective SPI1IE bit in the IEC0

register.

c)

Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.

3.

Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.

4.

Clear the SMP bit.

5.

If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SS1 pin.

6.

Clear the SPIROV bit (SPI1STAT<6>).

7.

Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).

8.

Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).

Internal Data Bus

SDI1

SDO1

SS1/FSYNC1

SCK1

SPI1SR

bit 0

Shift Control

Edge

Select

F

CY

Enable 

 Sync

SPI1BUF

Control

Transfer

Transfer

Write SPI1BUF

Read SPI1BUF

16

SPI1CON1<1:0>

SPI1CON1<4:2>

Master Clock

Clock

Control

Primary

1:1/4/16/64

Prescaler

Secondary

Prescaler

1:1 to 1:8

8-Level FIFO

Receive Buffer

8-Level FIFO

Transmit Buffer