Microchip Technology MCP9800DM-DL2 Data Sheet

Page of 4
 2007-2011 Microchip Technology Inc.
DS80331B-page 1
MCP9800/1/2/3
The MCP9800/1/2/3 parts you have received conform
functionally to the MCP9800/1/2/3 Data Sheet
(DS21909B), except for the anomalies described
below.
All of the issues listed here will be addressed in future
revisions of the MCP9800/1/2/3 silicon.
Contact Microchip for the latest Silicon fix.
1.
Module: Device Internal Latch-up at 
Higher Temperatures
The MCP9800/1/2/3 devices may latch-up during
I
2
C™ communication at high temperatures. This is
caused by the internal I
2
C interface slew control
circuit.
At temperatures >80°C (typically), High-to-Low
transition <500 ns on the SDA or SCL lines causes
the slew control circuit to latch-up. 
Work around
Connect a capacitor across the SDA and SCL
pull-up resistors so that the SDA and SCL fall
time is >500 ns. For example, use 5 k
/0.01 µf.
Date Codes that pertain to this issue:
This issue concerns the devices produced on or
before 718. This issue is fixed in devices with a
date code of 721.
2.
Module: POR Active During Oneshot 
Mode
At high temperatures the MCP9800/1/2/3 may
reset while waking up from the Oneshot mode.
All registers may be set at the power-up default
states. 
Work around
Shutdown and wake the device using the Shut-
down bit in the Configuration register.
Date Codes that pertain to this issue:
This issue concerns the devices produced on or
before 718. This issue is fixed in devices with a
date code of 721.
Clarification/Corrections to the Data 
Sheet:
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS21909B):
None at this time.
MCP9800/1/2/3 Rev. A Silicon/Data Sheet Errata