Microchip Technology Microstick for the 3V PIC24F K-series DM240013-1 DM240013-1 Data Sheet
Product codes
DM240013-1
2011 Microchip Technology Inc.
DS31037B-page 145
PIC24F16KL402 FAMILY
REGISTER 17-7:
SSPxCON3: MSSPx CONTROL REGISTER 3 (I
2
C™ MODE)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACKTIM
(
)
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented:
Read as ‘0’
bit 7
ACKTIM:
Acknowledge Time Status bit
1
= Indicates the I
2
C bus is in an Acknowledge sequence, set on the 8
th
falling edge of the SCLx clock
0
= Not an Acknowledge sequence, cleared on 9
th
rising edge of SCLx clock
bit 6
PCIE
: Stop Condition Interrupt Enable bit
1
= Enable interrupt on detection of Stop condition
0
= Stop detection interrupts are disabled
bit 5
SCIE
: Start Condition Interrupt Enable bit
1
= Enable interrupt on detection of Start or Restart conditions
0
= Start detection interrupts are disabled
(
)
bit 4
BOEN:
Buffer Overwrite Enable bit
I.
2
C Master mode:
This bit is ignored.
I
I
2
C Slave mode:
1
= SSPxBUF is updated and an ACK is generated for a received address/data byte, ignoring the state
of the SSPxOV bit only if the BF bit = 0
0
= SSPxBUF is only updated when SSPxOV is clear
bit 3
SDAHT:
SDAx Hold Time Selection bit
1
= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0
= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2
SBCDE:
Slave Mode Bus Collision Detect Enable bit (Slave mode only)
1
= Enables slave bus collision interrupts
0
= Slave bus collision interrupts are disabled
bit 1
AHEN:
Address Hold Enable bit (Slave mode only)
1
= Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0
= Address holding is disabled
bit 0
DHEN:
Data Hold Enable bit (Slave mode only)
1
= Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
of the SSPxCON1 register and SCLx is held low.
0
= Data holding is disabled
Note 1:
This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as
enabled.
enabled.
2:
The ACKTIM status bit is active only when the AHEN bit or DHEN bit is set.