Microchip Technology Microstick for the 3V PIC24F K-series DM240013-1 DM240013-1 Data Sheet
Product codes
DM240013-1
PIC24F16KL402 FAMILY
DS31037B-page 31
2011 Microchip Technology Inc.
4.0
MEMORY ORGANIZATION
As Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and bussing. This architecture also
allows the direct access of program memory from the
data space during code execution.
microcontrollers feature separate program and data
memory space and bussing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1
Program Address Space
The program address memory space of the
PIC24F16KL402 family is 4M instructions. The space is
addressable by a 24-bit value derived from either the
23-bit Program Counter (PC) during program execution,
or from a table operation or data space remapping, as
described in
PIC24F16KL402 family is 4M instructions. The space is
addressable by a 24-bit value derived from either the
23-bit Program Counter (PC) during program execution,
or from a table operation or data space remapping, as
described in
.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24F16KL402 family of
devices are shown in
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24F16KL402 family of
devices are shown in
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES
000000h
0000FEh
000002h
000100h
F8000Eh
F80010h
FEFFFEh
FFFFFFh
000004h
000200h
0001FEh
000104h
C
onf
igur
at
ion M
em
or
y S
pace
Us
er
Me
mo
ry
S
pa
ce
Note:
Memory areas are not displayed to scale.
Reset Address
Device Config Registers
DEVID (2)
GOTO
Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24F04KLXXX
FF0000h
F80000h
800000h
7FFFFFh
Reserved
Unimplemented
Read ‘0’
Reset Address
DEVID (2)
GOTO
Instruction
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24F16KLXXX
Device Config Registers
Unique ID
Unimplemented
Read ‘0’
002BFEh
7FFE00h
Data EEPROM
Flash
Program Memory
(5632 instructions)
Flash
Program Memory
(1408 instructions)
0015FEh
000AFEh
Reset Address
Device Config Registers
DEVID (2)
GOTO
Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24F08KL2XX
Reserved
Unimplemented
Read ‘0’
Flash
Program Memory
(2816 instructions)
(512 bytes)
7FFF00h
Reset Address
Device Config Registers
DEVID (2)
GOTO
Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24F08KL3XX
Reserved
Unimplemented
Read ‘0’
Data EEPROM
Flash
Program Memory
(2816 instructions)
(256 bytes)
Reset Address
Device Config Registers
DEVID (2)
GOTO
Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24F08KL4XX
Reserved
Unimplemented
Read ‘0’
Data EEPROM
Flash
Program Memory
(2816 instructions)
(512 bytes)
800802h
800808h
800800h
80080Ah
Reserved
Reserved
Reserved
Unique ID
Unique ID
Unique ID
Unique ID
Reserved
Reserved
Reserved
Reserved