Microchip Technology Microstick for the 3V PIC24F K-series DM240013-1 DM240013-1 Data Sheet

 2011 Microchip Technology Inc.

DS31037B-page 63

7.2.1

POR AND LONG OSCILLATOR 
START-UP TIMES

The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer (OST) has not 

expired (if a crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system.
Therefore, the oscillator and PLL start-up delays must
be considered when the Reset delay time must be
known. 

7.2.2

FAIL-SAFE CLOCK MONITOR 
(FSCM) AND DEVICE RESETS

If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).

Most of the Special Function Registers (SFRs)
associated with the PIC24F CPU and peripherals are
reset to a particular value at a device Reset. The SFRs
are grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, will
depend on the type of Reset and the programmed
values of the FNOSC bits in the Flash Configuration
Word (FOSCSEL); see 

. The RCFGCAL and

NVMCON registers are only affected by a POR.

PIC24F16KL402 family devices implement a BOR
circuit, which provides the user several configuration
and power-saving options. The BOR is controlled by
the BORV<1:0> and BOREN<1:0> Configuration bits
(FPOR<6:5,1:0>). There are a total of four BOR
configurations, which are provided in 

.

The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of V

DD

 below the set threshold point will

reset the device. The chip will remain in BOR until V

DD

rises above the threshold.
If the Power-up Timer is enabled, it will be invoked after
V

DD

 rises above the threshold. Then, it will keep the chip

in Reset for an additional time delay, T

PWRT

, if V

DD

drops below the threshold while the power-up timer is
running. The chip goes back into a BOR and the
Power-up Timer will be initialized. Once V

DD

 rises above

the threshold, the Power-up Timer will execute the
additional time delay.
BOR and the Power-up Timer (PWRT) are indepen-
dently configured. Enabling the BOR Reset does not
automatically enable the PWRT.

7.4.1

SOFTWARE ENABLED BOR

When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<13>). Setting SBOREN
enables the BOR to function, as previously described.
Clearing the SBOREN disables the BOR entirely. The
SBOREN bit only operates in this mode; otherwise, it is
read as ‘0’.
Placing BOR under software control gives the user the
additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change the BOR configuration. It also allows the user
to tailor the incremental current that the BOR
consumes. While the BOR current is typically very
small, it may have some impact in low-power
applications.

Even when the BOR is under software
control, the BOR Reset voltage level is still
set by the BORV<1:0> Configuration bits;
it can not be changed in software.