Microchip Technology MCP1630RD-DDBK3 Data Sheet
MCP1630/MCP1630V
DS21896C-page 12
2004-2013 Microchip Technology Inc.
4.0
DETAILED DESCRIPTION
4.1
Device Overview
The MCP1630 is comprised of a high-speed compara-
tor, high-bandwidth amplifier and logic gates that can
be combined with a PIC MCU to develop an advanced
programmable power supply. The oscillator and refer-
ence voltage inputs are generated by the PIC MCU so
that switching frequency, maximum duty cycle and out-
put voltage are programmable. Refer to Figure 4-1.
tor, high-bandwidth amplifier and logic gates that can
be combined with a PIC MCU to develop an advanced
programmable power supply. The oscillator and refer-
ence voltage inputs are generated by the PIC MCU so
that switching frequency, maximum duty cycle and out-
put voltage are programmable. Refer to Figure 4-1.
4.2
PWM
The V
EXT
output of the MCP1630/V is determined by
the output level of the internal high-speed comparator
and the level of the external oscillator. When the oscil-
lator level is high, the PWM output (V
and the level of the external oscillator. When the oscil-
lator level is high, the PWM output (V
EXT
) is forced low.
When the external oscillator is low, the PWM output is
determined by the output level of the internal high-
speed comparator. During UVLO, the V
determined by the output level of the internal high-
speed comparator. During UVLO, the V
EXT
pin is held
in the low state. During overtemperature operation, the
V
V
EXT
pin is high-impedance (100 k
to ground).
4.3
Normal Cycle by Cycle Control
The beginning of a cycle is defined when OSC IN tran-
sitions from a high state to a low state. For normal oper-
ation, the state of the high-speed comparator output
(R) is low and the Q output of the latch is low. On the
OSC IN high-to-low transition, the S and R inputs to the
high-speed latch are both low and the Q output will
remain unchanged (low). The output of the OR gate
(V
sitions from a high state to a low state. For normal oper-
ation, the state of the high-speed comparator output
(R) is low and the Q output of the latch is low. On the
OSC IN high-to-low transition, the S and R inputs to the
high-speed latch are both low and the Q output will
remain unchanged (low). The output of the OR gate
(V
DRIVE
) will transition from a high state to a low state,
turning on the internal P-channel drive transistor in the
output stage of the PWM. This will change the PWM
output (V
output stage of the PWM. This will change the PWM
output (V
EXT
) from a low state to a high state, turning
on the power-train external switch and ramping current
in the power-train magnetic device.
in the power-train magnetic device.
The sensed current in the magnetic device is fed into
the CS input (shown as a ramp) and increases linearly.
Once the sensed current ramp (MCP1630) reaches the
same voltage level as 1/3 of the EA output, the compar-
ator output (R) changes states (low-to-high) and resets
the PWM latch. The Q output transitions from a low
state to a high state, turning on the N-channel MOSFET
in the output stage, which turns off the V
the CS input (shown as a ramp) and increases linearly.
Once the sensed current ramp (MCP1630) reaches the
same voltage level as 1/3 of the EA output, the compar-
ator output (R) changes states (low-to-high) and resets
the PWM latch. The Q output transitions from a low
state to a high state, turning on the N-channel MOSFET
in the output stage, which turns off the V
EXT
drive to the
external MOSFET driver terminating the duty cycle.
The OSC IN will transition from a low state to a high
state while the V
The OSC IN will transition from a low state to a high
state while the V
EXT
pin remains unchanged. If the CS
input ramp had never reached the same level as 1/3 of
the error amplifier output, the low-to-high transition on
OSC IN would terminate the duty cycle and this would
be considered maximum duty cycle. In either case,
while OSC IN is high, the V
the error amplifier output, the low-to-high transition on
OSC IN would terminate the duty cycle and this would
be considered maximum duty cycle. In either case,
while OSC IN is high, the V
EXT
drive pin is low, turning
off the external power-train switch. The next cycle will
start on the transition of the OSC IN pin from a high
state to a low state.
start on the transition of the OSC IN pin from a high
state to a low state.
For Voltage mode or Average Current mode applica-
tions that utilize a large signal ramp at the CS input, the
MCP1630V is used to provide more signal (2.7V typ.).
The operation of the PWM does not change.
tions that utilize a large signal ramp at the CS input, the
MCP1630V is used to provide more signal (2.7V typ.).
The operation of the PWM does not change.
4.4
Error Amp/Comparator Current
Limit Function
Limit Function
The internal amplifier is used to create an error output
signal that is determined by the external V
signal that is determined by the external V
REF
input and
the power supply output fed back into the FB pin. The
error amplifier output is rail-to-rail and clamped by a
precision 2.7V. The output of the error amplifier is then
divided down 3:1 (MCP1630) and connected to the
inverting input of the high-speed comparator. Since the
maximum output of the error amplifier is 2.7V, the max-
imum input to the inverting pin of the high-speed com-
parator is 0.9V. This sets the peak current limit for the
switching power supply.
error amplifier output is rail-to-rail and clamped by a
precision 2.7V. The output of the error amplifier is then
divided down 3:1 (MCP1630) and connected to the
inverting input of the high-speed comparator. Since the
maximum output of the error amplifier is 2.7V, the max-
imum input to the inverting pin of the high-speed com-
parator is 0.9V. This sets the peak current limit for the
switching power supply.
For the MCP1630V, the maximum error amplifier out-
put is still 2.7V. However, the resistor divider is
removed, raising the maximum input signal level at the
high-speed comparator inverting input (CS) to 2.7V.
put is still 2.7V. However, the resistor divider is
removed, raising the maximum input signal level at the
high-speed comparator inverting input (CS) to 2.7V.
As the output load current demand increases, the error
amplifier output increases, causing the inverting input
pin of the high-speed comparator to increase.
Eventually, the output of the error amplifier will hit the
2.7V clamp, limiting the input of the high-speed com-
parator to 0.9V max (MCP1630). Even if the FB input
continues to decrease (calling for more current), the
inverting input is limited to 0.9V. By limiting the inverting
input to 0.9V, the current-sense input (CS) is limited to
0.9V, thus limiting the output current of the power
supply.
amplifier output increases, causing the inverting input
pin of the high-speed comparator to increase.
Eventually, the output of the error amplifier will hit the
2.7V clamp, limiting the input of the high-speed com-
parator to 0.9V max (MCP1630). Even if the FB input
continues to decrease (calling for more current), the
inverting input is limited to 0.9V. By limiting the inverting
input to 0.9V, the current-sense input (CS) is limited to
0.9V, thus limiting the output current of the power
supply.
For Voltage mode control, the error amplifier output will
increase as input voltage decreases. A voltage ramp is
used instead of sensed inductor current at the CS input
of the MCP1630V. The 3:1 internal error amplifier out-
put resistor divider is removed in the MCP1630V option
to increase the maximum signal level input to 2.7V
(typ.).
increase as input voltage decreases. A voltage ramp is
used instead of sensed inductor current at the CS input
of the MCP1630V. The 3:1 internal error amplifier out-
put resistor divider is removed in the MCP1630V option
to increase the maximum signal level input to 2.7V
(typ.).
4.5
0% Duty Cycle Operation
The duty cycle of the V
EXT
output is capable of reach-
ing 0% when the FB pin is held higher than the V
REF
pin
(inverting error amplifier). This is accomplished by the
rail-to-rail output capability of the error amplifier and the
offset voltage of the high-speed comparator. The mini-
mum error amplifier output voltage, divided by three, is
less than the offset voltage of the high-speed compar-
ator. In the case where the output voltage of the con-
verter is above the desired regulation point, the FB
input will be above the V
rail-to-rail output capability of the error amplifier and the
offset voltage of the high-speed comparator. The mini-
mum error amplifier output voltage, divided by three, is
less than the offset voltage of the high-speed compar-
ator. In the case where the output voltage of the con-
verter is above the desired regulation point, the FB
input will be above the V
REF
input and the error ampli-
fier will be pulled to the bottom rail (GND). This low
voltage is divided down 3:1 by the 2R and 1R resistor
(MCP1630) and connected to the input of the high-
speed comparator. This voltage will be low enough so
that there is no triggering of the comparator, allowing
narrow pulse widths at V
voltage is divided down 3:1 by the 2R and 1R resistor
(MCP1630) and connected to the input of the high-
speed comparator. This voltage will be low enough so
that there is no triggering of the comparator, allowing
narrow pulse widths at V
EXT
.