Microchip Technology DV164136 Data Sheet

© 2009 Microchip Technology Inc.

DS80343B-page 1

The PIC18F6627/6722/8627/8722 Rev. B1 parts you
have received conform functionally to the Device Data
Sheet (DS39646C), except for the anomalies
described below. Any Data Sheet Clarification issues
related to the PIC18F6627/6722/8627/8722 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.

The following silicon errata apply only to
PIC18F6627/6722/8627/8722 devices with these
Device/Revision IDs: 

All of the issues listed here will be addressed in future
revisions of the PIC18F6627/6722/8627/8722 silicon.

In SPI mode, the Buffer Full flag (BF bit in the
SSPxSTAT register), the Write Collision Detect bit
(WCOL in SSPxCON1) and the Receive Overflow
Indicator bit (SSPOV in SSPxCON1) are not reset
upon disabling the SPI module (by clearing the
SSPEN bit in the SSPxCON1 register).

For example, if SSPxBUF is full (BF bit is set), and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.

Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.

All engineering and production devices.

PWM output of 10-bit resolution is not available for
either CCP4 or CCP5 when Timer4 is being used
as the PWM time base (T3CON<6,3> = 01, 10 or
11

) for the PWM mode (CCPxCON<3:2> = 11).

For 10-bit resolution, use Timer2 as the PWM time
base (T3CON<6,3> = 00).

For 8-bit resolution, use Timer4 or Timer2 as the
PWM time base and set the two LSBs to ‘00’
(CCPxCON<5:4> = 00).

All engineering and production devices.

In extremely rare cases, when configured for I

2

C™

slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt has
occurred.

For SSP1BUF, the flag bit is SSP1IF (PIR1<3>).
For SSP2BUF, the flag bit is SSP2IF (PIR3<7>).

The issue can be resolved in either of these ways:

• Prior to the I

2

C slave reception, enable the 

clock-stretching feature.

This is done by setting the SEN bit
(SSP1CON2<0>).

• Each time the SSPxIF bit is set, read the 

SSPxBUF before the first rising clock edge of 
the next byte being received.

All engineering and production devices.

PIC18F6627

0001 0011 110

0 0010

PIC18F6722

0001 0100 000

0 0010

PIC18F8627

0001 0011 111

0 0010

PIC18F8722

0001 0100 001

0 0010

The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.