Microchip Technology MCP3901EV-MCU16 Data Sheet
MCP3901
DS22192D-page 30
© 2011 Microchip Technology Inc.
5.8
Power-on Reset
The MCP3901 contains an internal POR circuit that
monitors analog supply voltage AV
monitors analog supply voltage AV
DD
during operation.
The typical threshold for a power-up event detection is
4.2V ±5%. The POR circuit has a built-in hysteresis for
improved transient spikes immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
ceramic and 10 µF tantalum) should be mounted as
close as possible to the AV
4.2V ±5%. The POR circuit has a built-in hysteresis for
improved transient spikes immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
ceramic and 10 µF tantalum) should be mounted as
close as possible to the AV
DD
pin, providing additional
transient immunity.
illustrates the different conditions at
power-up and a power-down event in the typical
conditions. All internal DC biases are not settled until at
least 50 µs after system POR. Any DR pulses during
this time, after a system Reset, should be ignored. After
POR, DR pulses are present at the pin with all the
default conditions in the Configuration registers.
conditions. All internal DC biases are not settled until at
least 50 µs after system POR. Any DR pulses during
this time, after a system Reset, should be ignored. After
POR, DR pulses are present at the pin with all the
default conditions in the Configuration registers.
Both AV
DD
and DV
DD
power supplies are independent.
Since AV
DD
is the only power supply that is monitored,
it is highly recommended to power up DV
DD
first as a
power-up sequence. If AV
DD
is powered up first, it is
highly recommended to keep the RESET pin low during
the whole power-up sequence.
the whole power-up sequence.
FIGURE 5-4:
Power-on Reset Operation.
5.9
RESET Effect on Delta-Sigma
Modulator/SINC Filter
Modulator/SINC Filter
When the RESET pin is low, both ADCs will be in Reset
and output code, 0x0000h. The RESET pin performs a
Hard Reset (DC biases still on, part ready to convert)
and clears all charges contained in the Delta-Sigma
modulators. The comparators’ output is ‘0011’ for each
ADC.
and output code, 0x0000h. The RESET pin performs a
Hard Reset (DC biases still on, part ready to convert)
and clears all charges contained in the Delta-Sigma
modulators. The comparators’ output is ‘0011’ for each
ADC.
The SINC filters are all reset, as well as their double
output buffers. This pin is independent of the serial
interface. It brings the CONFIG registers to the default
state. When RESET is low, any write with the SPI
interface will be disabled and will have no effect. All
output pins (SDO, DR, MDAT0/1) are high-impedance,
and no clock is propagated through the chip.
output buffers. This pin is independent of the serial
interface. It brings the CONFIG registers to the default
state. When RESET is low, any write with the SPI
interface will be disabled and will have no effect. All
output pins (SDO, DR, MDAT0/1) are high-impedance,
and no clock is propagated through the chip.
5.10
Phase Delay Block
The MCP3901 incorporates a phase delay generator
which ensures that the two ADCs are converting the
inputs with a fixed delay between them. The two ADCs
are synchronously sampling but the averaging of
modulator outputs is delayed. Therefore, the SINC filter
outputs (thus, the ADC outputs) show a fixed phase
delay, as determined by the PHASE register setting.
which ensures that the two ADCs are converting the
inputs with a fixed delay between them. The two ADCs
are synchronously sampling but the averaging of
modulator outputs is delayed. Therefore, the SINC filter
outputs (thus, the ADC outputs) show a fixed phase
delay, as determined by the PHASE register setting.
The PHASE register (PHASE<7:0>) is a 7 bit + sign,
MSB first, two’s complement register that indicates how
much phase delay there is to be between Channel 0
and Channel 1. The reference channel for the delay is
Channel 1 (typically the voltage channel for power
metering applications). When PHASE<7:0> are
positive, Channel 0 is lagging versus Channel 1. When
PHASE<7:0> are negative, Channel 0 is leading
versus Channel 1. The amount of delay between two
ADC conversions is given by the following formula:
MSB first, two’s complement register that indicates how
much phase delay there is to be between Channel 0
and Channel 1. The reference channel for the delay is
Channel 1 (typically the voltage channel for power
metering applications). When PHASE<7:0> are
positive, Channel 0 is lagging versus Channel 1. When
PHASE<7:0> are negative, Channel 0 is leading
versus Channel 1. The amount of delay between two
ADC conversions is given by the following formula:
EQUATION 5-5:
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration with MCLK = 4 MHz.
1 µs in the default configuration with MCLK = 4 MHz.
The data ready signals are affected by the phase delay
settings. Typically, the time difference between the data
ready pulses of Channel 0 and Channel 1 is equal to
the phase delay setting.
settings. Typically, the time difference between the data
ready pulses of Channel 0 and Channel 1 is equal to
the phase delay setting.
AV
DD
5V
4.2V
4V
Device
Mode
Reset
Proper
Operation
Reset
Time
50 µs
0V
t
POR
Note:
A detailed explanation of the Data Ready
pin (DR) with phase delay is present in
pin (DR) with phase delay is present in
Delay
Phase Register Code
DMCLK
--------------------------------------------------
=