Microchip Technology MCP3422EV Data Sheet

© 2009 Microchip Technology Inc.

DS22088C-page 11

The descriptions of the pins are listed in 

 

CHn+ and CHn- are differential input pins for
channel n. The user can also connect CHn- pin to V

SS

for a single-ended operation. See 

differential and single-ended connection examples. 

The maximum voltage range on each differential input
pin is from V

SS

-0.3V to V

DD

+0.3V. Any voltage below or

above this range will cause leakage currents through
the Electrostatic Discharge (ESD) diodes at the input
pins.

This ESD current can cause unexpected performance
of the device. The input voltage at the input pins should
be within the specified operating range defined in
Section 1.0 “Electrical Characteristics” and
Section 4.0 “Description of Device Operation”. 

See  Section 4.5 “Input Voltage Range” for more
details of the input voltage range. 

 shows the input structure of the device. The

device uses a switched capacitor input stage at the
front end. C

PIN

 is the package pin capacitance and

typically about 4 pF. D

1

 and D

2

 are the ESD diodes.

C

SAMPLE

 is the differential input sampling capacitor.

 

V

DD

 is the power supply pin for the device. This pin

requires an appropriate bypass ceramic capacitor of
about 0.1 µF to ground to attenuate high frequency
noise presented in application circuit board. An
additional 10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate current spike
noises. The supply voltage (V

DD

) must be maintained

in the 2.7V to 5.5V range for specified operation. 

V

SS

 is the ground pin and the current return path of the

device. The user must connect the V

SS

 pin to a ground

plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the V

SS

 pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit
board. 

DFN

MSOP,

SOIC

DFN

MSOP

SOIC, 

TSSOP

1

1

1

1

1

CH1+

Positive Differential Analog Input Pin of Channel 1

2

2

2

2

2

CH1-

Negative Differential Analog Input Pin of Channel 1

7

7

4

4

3

CH2+

Positive Differential Analog Input Pin of Channel 2

8

8

5

5

4

CH2-

Negative Differential Analog Input Pin of Channel 2

6

6

3

3

5

V

SS

Ground Pin

3

3

6

6

6

V

DD

Positive Supply Voltage Pin

4

4

7

7

7

SDA

Bidirectional Serial Data Pin of the I

2

C Interface

5

5

8

8

8

SCL

Serial Clock Pin of the I

2

C Interface

—

—

9

9

9

Adr0

I

2

C Address Selection Pin. See Section 5.3.2.

—

—

10

10

10

Adr1

I

2

C Address Selection Pin. See Section 5.3.2.

—

—

—

—

11

CH3+

Positive Differential Analog Input Pin of Channel 3

—

—

—

—

12

CH3-

Negative Differential Analog Input Pin of Channel 3

—

—

—

—

13

CH4+

Positive Differential Analog Input Pin of Channel 4

—

—

—

—

14

CH4-

Negative Differential Analog Input Pin of Channel 4

9

—

11

—

—

EP

Exposed Thermal Pad (EP); must be connected to 
V

SS

.