Microchip Technology AC160214 Data Sheet
2010-2012 Microchip Technology Inc.
DS41414D-page 305
PIC16(L)F1946/47
FIGURE 25-5:
ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RXx/DTx pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCxREG
RCxIF
(Interrupt Flag)
(Interrupt Flag)
OERR bit
CREN
Word 1
RCxREG
Word 2
RCxREG
Stop
bit
Note:
This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.
word, causing the OERR (overrun) bit to be set.
RCIDL
TABLE 25-2:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUD1CON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
BAUD2CON
ABDOVF
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
—
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE4
—
—
RC2IE
TX2IE
—
—
BCL2IE
SSP2IE
PIR1
—
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIR4
—
—
RC2IF
TX2IF
—
—
BCL2IF
SSP2IF
RC1REG
EUSART1 Receive Register
*
RC1STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RC2REG
EUSART2 Receive Register
*
RC2STA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SP1BRGL
EUSART1 Baud Rate Generator, Low Byte
*
SP1BRGH
EUSART1 Baud Rate Generator, High Byte
*
SP2BRGL
EUSART2 Baud Rate Generator, Low Byte
*
SP2BRGH
EUSART2 Baud Rate Generator, High Byte
*
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TX1STA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
TX2STA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
*
Page provides register information.