Microchip Technology MA180025 Data Sheet

Page of 450
PIC18F87J90 FAMILY
DS39933D-page 144
 2010 Microchip Technology Inc.
12.1
Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
cycle (F
OSC
/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM (8-BIT MODE)               
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN
(1)
F
OSC
/4
Internal
Clock
On/Off
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR1ON
TMR1L
Set 
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
Prescaler
1, 2, 4, 8
Synchronize
Detect
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN
(1)
F
OSC
/4
Internal
Clock
1
0
2
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set 
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
Timer1 Clock Input
Prescaler
1, 2, 4, 8
Synchronize
Detect