Microchip Technology MA180025 Data Sheet
2010 Microchip Technology Inc.
DS39933D-page 173
PIC18F87J90 FAMILY
16.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F87J90 family devices have two CCP
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard capture,
compare and Pulse-Width Modulation (PWM) modes.
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard capture,
compare and Pulse-Width Modulation (PWM) modes.
Each CCP module contains two 8-bit registers that can
operate as two 8-bit Capture registers, two 8-bit
Compare registers or two PWM Master/Slave Duty
Cycle registers. For the sake of clarity, all CCP module
operation in the following sections is described with
respect to CCP2, but is equally applicable to CCP1.
operate as two 8-bit Capture registers, two 8-bit
Compare registers or two PWM Master/Slave Duty
Cycle registers. For the sake of clarity, all CCP module
operation in the following sections is described with
respect to CCP2, but is equally applicable to CCP1.
REGISTER 16-1:
CCPxCON: CCPx CONTROL REGISTER (CCP1, CCP2 MODULES)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM<3:0>: CCPx Module Mode Select bits
0000
= Capture/Compare/PWM disabled (resets CCPx module)
0001
= Reserved
0010
= Compare mode, toggle output on match (CCPxIF bit is set)
0011
= Reserved
0100
= Capture mode, every falling edge
0101
= Capture mode, every rising edge
0110
= Capture mode, every 4th rising edge
0111
= Capture mode, every 16th rising edge
1000
= Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
is set)
1001
= Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
is set)
1010
= Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011
= Compare mode: Special Event Trigger; reset timer; start A/D conversion on CCPx match
(CCPxIF bit is set)
(1)
11xx
= PWM mode
Note 1:
CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on a CCP1 match.