Microchip Technology MA180025 Data Sheet
2010 Microchip Technology Inc.
DS39933D-page 191
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17.3.3.3
M2 (Resistor Ladder with
Software Contrast)
Software Contrast)
M2 operation also uses the LCD regulator but disables
the charge pump. The regulator’s internal voltage refer-
ence remains active as a way to regulate contrast. It is
used in cases where the current requirements of the
LCD exceed the capacity of the regulator’s charge
pump.
In this configuration, the LCD bias voltage levels are
created by an external resistor voltage divider,
connected across LCDBIAS0 through LCDBIAS3, with
the top of the divider tied to V
the charge pump. The regulator’s internal voltage refer-
ence remains active as a way to regulate contrast. It is
used in cases where the current requirements of the
LCD exceed the capacity of the regulator’s charge
pump.
In this configuration, the LCD bias voltage levels are
created by an external resistor voltage divider,
connected across LCDBIAS0 through LCDBIAS3, with
the top of the divider tied to V
DD
potential at the bottom of the ladder is determined by
the LCD regulator’s voltage reference, tied internally to
LCDBIAS0. The bias type is determined by the volt-
ages on the LCDBIAS pins, which are controlled by the
the LCD regulator’s voltage reference, tied internally to
LCDBIAS0. The bias type is determined by the volt-
ages on the LCDBIAS pins, which are controlled by the
configuration of the resistor ladder. Most applications
using M2 will use a 1/3 or 1/2 Bias type. While Static
Bias can also be used, it offers extremely limited
contrast range and additional current consumption
over other bias generation modes.
Like M1, the LCDBIAS bits can be used to control con-
trast, limited by the level of V
using M2 will use a 1/3 or 1/2 Bias type. While Static
Bias can also be used, it offers extremely limited
contrast range and additional current consumption
over other bias generation modes.
Like M1, the LCDBIAS bits can be used to control con-
trast, limited by the level of V
DD
supplied to the device.
Also, since there is no capacitor required across
V
V
LCAP
1 and V
LCAP
2, these pins are available as digital
I/O ports, RG2 and RG3.
M2 is selected by clearing the CKSEL<1:0> bits and
setting the CPEN bit.
M2 is selected by clearing the CKSEL<1:0> bits and
setting the CPEN bit.
FIGURE 17-4:
RESISTOR LADDER CONNECTIONS FOR M2 CONFIGURATION
LCDBIAS3
Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer
based on the actual LCD specifications.
Bias Level at Pin
Bias Type
1/2 Bias
1/3 Bias
LCDBIAS0
(Internal Low Reference Voltage)
(Internal Low Reference Voltage)
LCDBIAS1
1/2 V
BIAS
1/3 V
BIAS
LCDBIAS2
1/2 V
BIAS
2/3 V
BIAS
LCDBIAS3
V
BIAS
(up to AV
DD
)
V
BIAS
(up to AV
DD
)
10 k
(1)
10 k
(1)
1/2 Bias
1/3 Bias
LCDBIAS2
LCDBIAS1
LCDBIAS0
AV
DD
10 k
(1)
10 k
(1)
10 k
(1)
V
DD
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