Microchip Technology MA180025 Data Sheet
2010 Microchip Technology Inc.
DS39933D-page 217
PIC18F87J90 FAMILY
18.3.7
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
18.3.8
SLAVE SELECT
SYNCHRONIZATION
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). When the SS pin is low,
transmission and reception are enabled and the SDO
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). When the SS pin is low,
transmission and reception are enabled and the SDO
pin is driven. When the SS pin goes high, the SDO pin
is no longer driven, even if in the middle of a transmitted
byte, and becomes a floating output. External
pull-up/pull-down resistors may be desirable
depending on the application.
is no longer driven, even if in the middle of a transmitted
byte, and becomes a floating output. External
pull-up/pull-down resistors may be desirable
depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 18-4:
SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with
the
SS pin control enabled
(SSPCON1<3:0> = 0100), the SPI
module will reset if the SS pin is set to V
module will reset if the SS pin is set to V
DD
.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO
bit 7
bit 6
bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
Next Q4 Cycle
after Q2
after Q2