Microchip Technology MA180025 Data Sheet
PIC18F87J90 FAMILY
DS39933D-page 332
2010 Microchip Technology Inc.
TABLE 25-3:
SUMMARY OF WATCHDOG TIMER REGISTERS
REGISTER 25-9:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
REGSLP
(1)
—
—
—
—
—
—
SWDTEN
(2)
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
REGSLP: Voltage Regulator Low-Power Operation Enable bit
(1)
1
= On-chip regulator enters low-power operation when device enters Sleep mode
0
= On-chip regulator continues to operate normally in Sleep mode
bit 6-1
Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
(2)
1
= Watchdog Timer is on
0
= Watchdog Timer is off
Note 1:
The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
2:
This bit has no effect if the Configuration bit, WDTEN, is enabled.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset Values
on page
RCON
IPEN
—
CM
RI
TO
PD
POR
BOR
WDTCON
REGSLP
—
—
—
—
—
—
SWDTEN
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.