Microchip Technology MA180025 Data Sheet
PIC18F87J90 FAMILY
DS39933D-page 410
2010 Microchip Technology Inc.
28.5.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-4:
EXTERNAL CLOCK TIMING
TABLE 28-7:
EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
1A
F
OSC
External CLKI Frequency
(1)
DC
48
MHz
EC Oscillator mode
DC
10
ECPLL Oscillator mode
Oscillator Frequency
(1)
4
25
MHz
HS Oscillator mode
4
10
HSPLL Oscillator mode
1
T
OSC
External CLKI Period
(1)
20.8
—
ns
EC Oscillator mode
100
—
ECPLL Oscillator mode
Oscillator Period
(1)
40.0
250
ns
HS Oscillator mode
100
250
HSPLL Oscillator mode
2
T
CY
Instruction Cycle Time
(1)
83.3
—
ns
T
CY
= 4/F
OSC
, Industrial
3
T
OS
L,
T
OS
H
External Clock in (OSC1)
High or Low Time
High or Low Time
10
—
ns
HS Oscillator mode
4
T
OS
R,
T
OS
F
External Clock in (OSC1)
Rise or Fall Time
Rise or Fall Time
—
7.5
ns
HS Oscillator mode
Note 1: Instruction cycle period (T
CY
) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4
Q1
Q2
Q3
Q4
Q1
1
2
3
3
4
4