Microchip Technology MA180025 Data Sheet
2010 Microchip Technology Inc.
DS39933D-page 419
PIC18F87J90 FAMILY
FIGURE 28-12:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 28-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
T
SS
L2
SC
H,
T
SS
L2
SC
L
SS
to SCK or SCK Input
3 T
CY
—
ns
70A
T
SS
L2WB SS to write to SSPBUF
3 T
CY
—
ns
71
T
SC
H
SCK Input High Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30 —
ns
71A
Single Byte
40
—
ns
(Note 1)
72
T
SC
L
SCK Input Low Time
(Slave mode)
(Slave mode)
Continuous
1.25 T
CY
+ 30 —
ns
72A
Single Byte
40
—
ns
(Note 1)
73A
T
B
2
B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
CY
+ 40
—
ns
(Note 2)
74
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDI Data Input to SCK Edge
40
—
ns
75
T
DO
R
SDO Data Output Rise Time
—
25
ns
76
T
DO
F
SDO Data Output Fall Time
—
25
ns
77
T
SS
H2
DO
Z SS
to SDO Output High-Impedance
10
50
ns
78
T
SC
R
SCK Output Rise Time (Master mode)
—
25
ns
79
T
SC
F
SCK Output Fall Time (Master mode)
—
25
ns
80
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDO Data Output Valid after SCK Edge
—
50
ns
82
T
SS
L2
DO
V SDO Data Output Valid after SS
Edge
—
50
ns
83
T
SC
H2
SS
H,
T
SC
L2
SS
H
SS
after SCK Edge
1.5 T
CY
+ 40
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
(CKP = 0)
SCK
(CKP = 1)
(CKP = 1)
SDO
SDI
70
71
72
82
74
75, 76
MSb
bit 6 - - - - - - 1
LSb
77
bit 6 - - - - 1
LSb In
80
83
Note:
Refer to Figure 28-3 for load conditions.
MSb In