Microchip Technology MCP4728EV Data Sheet

© 2010 Microchip Technology Inc.

DS22187E-page 23

The MCP4728 device is a 12-bit 4-channel buffered
voltage output DAC with nonvolatile memory
(EEPROM). The user can program the EEPROM with
I

2

C address bits, configuration and DAC input data of

each channel. The device has an internal charge pump
circuit to provide the programming voltage of the
EEPROM.

When the device is first powered-up, it automatically
loads the stored data in its EEPROM to the DAC input
and output registers, and provides analog outputs with
the saved settings immediately. This event does not
require an LDAC or UDAC bit condition. After the
device is powered-up, the user can update the input
registers using I

2

C write commands. The analog

outputs can be updated with new register values if the
LDAC pin or UDAC bit is low. The DAC output of each
channel is buffered with a low power and precision
output amplifier. This amplifier provides a rail-to-rail
output with low offset voltage and low noise.

The device uses a resistor string architecture. The
resistor ladder DAC can be driven from V

DD

 or internal

V

REF

, depending on the reference selection. The user

can select internal (2.048V) or external reference (V

DD

)

for each DAC channel individually by software control.
The V

DD

 is used as the external reference. Each

channel is controlled and operated independently.

The device has a Power-Down mode feature. Most of
the circuit in each powered down channel are turned
off. Therefore, operating power can be saved
significantly by putting any unused channel to the
Power-Down mode.

The device contains an internal Power-on Reset (POR)
circuit that monitors power supply voltage (V

DD

) during

operation. This circuit ensures correct device start-up
at system power-up and power-down events.

If the power supply voltage is less than the POR
threshold (V

POR

= 2V, typical), all circuits are disabled

and there will be no analog output. When the V

DD

increases above the V

POR

, the device takes a reset

state. During the reset period, each channel uploads all
configuration and DAC input codes from EEPROM,
and analog output (V

OUT

) will be available accordingly.

This enables the device to return to the same state that
it was at the last write to the EEPROM, before it was
powered off. The POR status is monitored by the POR
status bit by using the I

2

C read command. See

 for the details of the POR status bit.

The device can be reset by two independent events: 

a)

by Power-on Reset 

b)

by I

2

C General Call Reset Command

Under the reset conditions, the device uploads the
EEPROM data into

 

both of the DAC input and output

registers simultaneously. The analog output voltage of
each channel is available immediately, regardless of
the LDAC and UDAC bit conditions.

The factory default settings for the EEPROM prior to
the device shipment are shown in

.

The DAC output is buffered with a low power precision
amplifier. This amplifier provides low offset voltage and
low noise, as well as rail-to-rail output.

The output amplifier can drive the resistive and high
capacitive loads without oscillation. The amplifier can
provide a maximum load current of 24 mA, which is
enough for most of programmable voltage reference
applications. Refer to 

 for the specifications of the output

amplifier.

4.3.1

PROGRAMMABLE GAIN BLOCK

The rail-to-rail output amplifier of each channel has
configurable gain option. When the internal voltage
reference is selected, the output amplifier gain has two
selection options: Gain of 1 or Gain of 2. 

When the external reference is selected (V

REF

= V

DD

),

the Gain of 2 option is disabled, and only the Gain of 1
is used by default. 

4.3.1.1

Resistive and Capacitive Loads

The analog output (V

OUT

) pin is capable of driving

capacitive loads up to 1000 pF in parallel with 5 k

Ω

load resistance. 

 shows the V

OUT

 vs.

Resistive Load.