Microchip Technology ARD00330 Data Sheet
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 267
PIC18F87J72 FAMILY
FIGURE 20-5:
ASYNCHRONOUS RECEPTION
TABLE 20-5:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR3
—
LCDIF
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
RTCCIF
52
PIE3
—
LCDIE
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
RTCCIE
IPR3
—
LCDIP
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG2
AUSART Receive Register
TXSTA2
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRG2
AUSART Baud Rate Generator Register
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RX2 (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG2
Word 2
RCREG2
Stop
bit
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.